Method and apparatus for setting and compensating read latency in a high speed DRAM
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson, Feng Lin
Life of this patent
Estimating the term…
Abstract
An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.
Claims105
A method of operating a memory device, said method comprising:
- generating an internal read clock signal from an external clock signal using a first signal processing path, said first signal processing path causing variations in the timing of said generated read clock signal;
- generating a read start signal in response to a received read command;
- passing said read start signal through a second signal processing path which replicates the variations in the timing of said generated read clock signal caused by the first signal processing path and producing a delayed start signal;
- and
- using said delayed start signal to synchronize the output of read data by said read clock at a read latch.
A method of operating a memory device, comprising:
- using an external clock signal as an input to a first delay lock loop to produce a read clock signal;
- passing a signal generated in response to receipt of a read command through a delay circuit slaved to said first delay lock loop to produce a delayed signal;
- and
- using said delayed signal and read clock signal to output read data from a memory array of said memory device.
A memory device comprising:
- a first signal processing path for producing an internal read clock signal from an external clock signal, said first signal processing path imparting timing variations on said read clock signal;
- a second signal processing path for producing a delayed start signal from a received read command, said second signal processing path imparting said timing variations to said delayed start signal;
- and
- a data flow control circuit for outputting read data in response to said delayed start signal and read clock signal.
A memory device comprising:
- a delay lock loop for processing a read clock signal from an external clock signal;
- a delay circuit synchronized with said delay lock loop for producing a delayed start signal from a start signal generated in response to receipt of a read command;
- a read data latch;
- a data pass circuit for passing data from a memory array to said read data latch;
- and
- an enable circuit responsive to said delayed start signal for enabling data from said data pass circuit to be read out by said read clock signal after a predetermined number of cycles of said read clock signal are counted.
A processor system comprising
- a processor;
- and
- a memory device for exchanging data with said processor, said memory device comprising:
- a first signal processing path for producing an internal read clock signal from an external clock signal said first signal processing path imparting timing variations on said read clock signal;
- a second signal processing path for producing a delayed start signal from a received read command, said second signal processing path imparting said timing variations to said delayed start signal;
- and
- a data flow control circuit for outputting read data in response to said delayed start signal and read clock signal.
A processor system comprising:
- a processor;
- and
- a memory device for exchanging data with said processor, said memory device comprising:
- a delay lock loop for processing a read clock signal from an external clock signal;
- a delay circuit synchronized with said delay lock loop for producing a delayed start signal from a start signal generated in response to receipt of a read command;
- a read data latch;
- a data pass circuit for passing data from a memory array to said read data latch;
- and
- an enable circuit responsive to said delayed start signal for enabling data from said data pass circuit to be read out by said read clock signal after a predetermined number of cycles of said read clock signal are counted.
Dependencies are inferred from the claim text.