Compiled variable internal self time memory
AssigneeLSI Logic Corporation
InventorsSteven M. Peterson, Sifang Wu, Mai Mac Lennan, Carl A. Monzel
Life of this patent
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Abstract
A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.
Claims23
A method for controlling bit line separation of a memory when the memory is accessed by controlling the number of core cells used for driving a self time column of the memory, comprising:
- selecting a variable within a compiler compiling the memory for varying the number of core cells used for driving the self time column of the memory;
- and
- tiling core cells of the memory according to the received variable during compilation of the memory so as to configure the self time column to have a number of core cells suitable for providing a desired self time bit line separation.
A self time circuit for a memory, comprising:
- a plurality of core cells within the memory;
- and
- a self time word line coupled to at least one core cell for activating the core cell;
- wherein the number of core cells coupled to the self time word line is set during compilation by a compiler by adjusting a variable of the compiler for controlling bit line separation of the memory when the memory is accessed.
A self time circuit for a memory, comprising:
- a plurality of core cells within the memory;
- and
- a plurality of self time word lines, each of the self time lines being coupled to at least one core cell for activating the core cell;
- wherein the number of core cells coupled to at least one of the self time word lines is set during compilation by a compiler by adjusting a variable of the compiler for controlling bit line separation of the memory when the memory is accessed.
A memory, comprising:
- a plurality of core cells;
- a plurality of self time word lines, each of the self time lines being coupled to at least one core cell for activating the core cell;
- a plurality of self time enable lines, each self time enable line being coupled to a common self time word line by a logic gate, the output of the logic gate being a self time word line,
- wherein the number of core cells coupled to at least one of the self time word lines is set during compilation by a compiler by adjusting a variable of the compiler for controlling bit line separation of the memory when the memory is accessed.
A self time circuit for a memory, comprising:
- a plurality of core cells within the memory;
- and
- means, coupled to the core cells, for activating the core cells;
- wherein the number of core cells coupled to the activating means is set during compilation by a compiler by adjusting a variable of the compiler for controlling bit line separation of the memory when the memory is accessed.
Dependencies are inferred from the claim text.