Semiconductor memory device

Abstract

A semiconductor memory device, comprising: a plurality of blocks arranged in line in a first direction, each block including a plurality of sections each having a cell group obtained by dividing a cell array composed of a plurality of cells and a cell group control circuit which controls read/write for the corresponding cell group and operates independently to each other, the plurality of sections being arranged in line in a second direction; data lines extending in the second direction and commonly connected to the plurality of sections in the same block, the data lines transferring data for the plurality of sections; and signal lines passing through the plurality of blocks and extending in the first direction, the signal lines transferring at least one of a control signal which controls read/write for the sections, an address signal which selects the sections, and the other signal transferred to the sections.

Dependencies are inferred from the claim text.