Semiconductor memory device with less data transfer delay time

A semiconductor memory device comprising:

• a memory cell array which has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses;
• a first even data bus connected with said even bank, wherein even read data is outputted from said even bank in response to a first control signal;
• a second even data bus;
• a first odd data bus connected with said odd bank, wherein odd read data is outputted from said odd bank in response to said first read control signal;
• a second odd data bus;
• a common data bus;
• a relaying unit provided between a set of said first even and odd data buses and a set of said second even and odd data buses to receive said even read data on said first even data bus to output said even read data to said second even data bus in response to a second read control signal, and to receive said odd read data on said first odd data bus to output said odd read data to said second odd data bus in response to said second read control signal;
• and
• an I/O circuit provided between said common data bus and the set of said second even and odd data buses to receive said even read data from said second even data bus and said odd read data from said second odd data bus, and to output one of said even read data and said odd read data to said common data bus and then outputs the other to said common data bus, in response to a third read control signal.