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US 6,687,180 B2Granted
Driver control circuit
AssigneeMicron Technology, Inc.
InventorsAdrian J. Drexler, Debra M. Bell
Life of this patent
Estimating the term…
Abstract
A memory device includes a plurality of memory banks and a plurality of bank drivers. Each of the bank drivers connects to a corresponding memory bank. During a memory operation, an input signal is driven to a selected memory bank by activating one more bank drivers but not all of the bank drivers.
Claims54
A memory device comprising:
- a plurality of memory banks;
- a plurality of drivers, each connecting to a corresponding one of the memory banks;
- and
- a plurality of driver enable circuits connected to the drivers for activating a subset of the drivers to pass a signal to be written into the memory banks, wherein the subset of the drivers includes a number of drivers that is less than a total number of the drivers.
1 more element
A memory device comprising:
- a plurality of memory banks;
- and
- a plurality of input paths, each connecting between a corresponding one of the memory banks and an internal node common to the input paths, the input paths including a plurality of driver enable circuits and a plurality of drivers to drive an input signal to be written into one of the memory banks to the memory banks via a subset of the input paths, wherein the subset of the input paths includes fewer drivers than a total number of the drivers.
A memory device comprising:
- a plurality of memory banks;
- a plurality of bank input nodes to receive a plurality of bank address signals for selecting one of the memory banks as a selected memory bank;
- a plurality of drivers, each connecting to one of the memory banks;
- and
- a plurality of driver enable circuits, each connecting between a corresponding one of the drivers and an internal node common to the driver enable circuits for passing an input signal to be written into the selected memory bank from the internal node to only the corresponding driver that connects to the selected memory bank, wherein each of the driver enable circuits includes a pass gate connected between the internal node and the corresponding driver.
2 more elements
A memory device comprising:
- a plurality of memory banks;
- one or more bank input nodes to receive one or more bank address signals for selecting one of the memory banks as a selected memory bank;
- a plurality of drivers, each connecting to a corresponding one of the memory banks;
- and
- a plurality of driver enable circuits connected to the drivers for passing an input signal to be written into the selected memory bank to the one driver that connects to the selected memory bank and for passing the input signal to one or more other drivers but not all of the drivers, wherein each of the driver enable circuits includes a pass gate connected to a corresponding driver.
2 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a plurality of memory banks;
- a plurality of drivers, each connecting to a corresponding one of the memory banks;
- and
- a plurality of driver enable circuits connected to the drivers for activating a subset of the drivers to pass a signal to be written into one of the memory banks to the memory banks, wherein the subset of the drivers includes a number of drivers that is less than a total number of the drivers.
4 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a plurality of memory banks;
- and
- a plurality input paths, each connecting between a corresponding one of the memory banks and an internal node common to the input paths, the input paths including a plurality of driver enable circuits a plurality of drivers to drive an input signal to be written into one of the memory banks to the memory banks via a subset of the input paths, wherein the subset of the input paths includes fewer drivers than a total number of the drivers.
3 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a plurality of memory banks;
- one or more bank input nodes to receive one or more bank address signals for selecting one of the memory banks as a selected memory bank;
- a plurality of drivers, each connecting to one of the memory banks;
- and
- a plurality of driver enable circuits, each connecting between a corresponding one of the drivers and an internal node common to the driver enable circuits for passing an input signal to be written into the selected memory bank from the internal node to only the corresponding driver that connects to the selected memory bank, wherein each of the driver enable circuits includes a pass gate connected between the internal node and the corresponding driver, wherein each of the drivers includes a plurality of inverters connected in series between one of the driver enable circuits and one of the memory banks.
5 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a plurality of memory banks;
- one or more bank input nodes to receive one or more bank address signals for selecting one of the memory banks as a selected memory bank;
- a plurality of drivers, each connecting to one of the memory banks;
- and
- a plurality of driver enable circuits, each connecting between a corresponding one of the drivers and an internal node common to the driver enable circuits for passing an input signal to be written into the selected memory bank from the internal node to only the corresponding driver that connects to the selected memory bank, wherein each of the driver enable circuits includes a pass gate connected between the internal node and the corresponding driver.
5 more elements
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a plurality of memory banks;
- one or more bank input nodes to receive one or more bank address signals for selecting one of the memory banks as a selected memory bank;
- a plurality of drivers, each connecting to a corresponding one of the memory banks;
- and
- a plurality of driver enable circuits connected to the drivers for passing an input signal to be written into the selected memory bank to the one driver that connects to the selected memory bank and to one or more other drivers but not all the drivers, wherein each of the driver enable circuits includes a pass gate connected to a corresponding driver.
5 more elements
A method of driving a signal, the method comprising:
- selecting a selected memory bank among a plurality of memory banks;
- passing an input signal to be written into the selected memory bank to an internal node common to a plurality of input paths connected to the memory banks, the input paths including a plurality of drivers;
- and
- passing the input signal from the internal node to the selected memory bank via a subset of the input paths, wherein the subset of the input paths includes fewer drivers than the total number of the drivers.
1 more element
A method of driving a signal, the method comprising:
- selecting a selected memory bank among a plurality of memory banks;
- passing an input signal to be written into the selected memory bank to a plurality of driver enable circuits connected to a plurality of drivers;
- activating a subset of the driver enable circuits, wherein the subset of the driver enable circuits includes a number of driver enable circuits that is less than a total number of the driver enable circuits;
- passing the input signal from the subset of the driver enable circuits to a subset of the drivers, wherein the subset of the drivers includes a number of drivers that is less than a total number of the drivers;
- and
- driving the input signal from the subset of the drivers to the selected memory bank.
3 more elements
Dependencies are inferred from the claim text.