Back to results
US 6,687,179 B2Granted
Method and system for writing data in an MRAM memory device
AssigneeMicron Technology, Inc.
InventorR. Jacob Baker
Life of this patent
Estimating the term…
Abstract
An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.
Claims94
A method of writing data to memory cells in an MRAM array, the array including a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line, the method comprising:
- applying a row current to a selected word line;
- applying a first column current to a selected bit line, the first column current being applied in a first direction;
- and
- applying second column currents to unselected bit lines adjacent the selected bit line, the second column currents being applied in a second direction that is opposite the first direction.
1 more element
A method of writing data to memory cells in an MRAM array, the array including a plurality of memory cells and the method comprising:
- generating a first magnetic field, the first magnetic field being applied to a selected memory cell;
- generating a second magnetic field, the second magnetic field being applied to the selected memory cell and to memory cells adjacent the selected memory cell;
- and
- generating a third magnetic field, the third magnetic field opposing the second magnetic field to reduce a net magnetic field applied to the memory cells adjacent the selected memory cell.
1 more element
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line.
2 more elements
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to receive a column current having a first direction applied on a selected bit line, and operable to apply column currents in a second direction opposite the first direction on at least one of unselected bit lines adjacent the selected bit line.
2 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM array coupled to the address decoder, control circuit, and read/write circuit;
- the array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line.
10 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on the a selected bit line.
15 more elements
An MRAM array comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network derives the currents applied on each unselected bit line from current applied on the selected bit line.
2 more elements
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network comprises a plurality of switches, each switch being coupled between a pair of adjacent bit lines, and each switch operable to couple the bit lines together responsive to a switch control signal being active and to isolate the bit lines responsive to the switch control signal being inactive, each switch having resistance when the switch control signal is active, and wherein the value of the resistance is selected to ensure a minimum portion of the current applied on the selected bit line is applied to each unselected bit line adjacent the selected bit line.
2 more elements
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network applies the column current on at least one unselected bit line adjacent the selected bit line.
2 more elements
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to receive a column current having a first direction applied on a selected bit line, and operable to apply column currents in a second direction opposite the first direction on at least one of unselected bit lines adjacent the selected bit line, wherein the switching network derives the currents applied on the unselected bit lines from the column current applied on the selected bit line.
2 more elements
An MRAM array, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to receive a column current having a first direction applied on a selected bit line, and operable to apply column currents in a second direction opposite the first direction on at least one of unselected bit lines adjacent the selected bit line, wherein the switching network applies the column currents in the second direction on all unselected bit lines in the array.
2 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM array coupled to the address decoder, control circuit, and read/write circuit;
- the array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network derives the column currents applied on each unselected bit line from the current applied on the selected bit line.
10 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM array coupled to the address decoder, control circuit, and read/write circuit;
- the array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network comprises a plurality of switches, each switch being coupled between a pair of adjacent bit lines, and each switch operable to couple the bit lines together responsive to a switch control signal being active and to isolate the bit lines responsive to the switch control signal being inactive, and further wherein each switch has resistance when the switch control signal is active, the value of the resistance being selected to ensure a minimum portion of the current applied on the selected bit line is applied to each unselected bit line adjacent the selected bit line.
10 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM array coupled to the address decoder, control circuit, and read/write circuit;
- the array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network applies the column current on at least one unselected bit line adjacent the selected bit line.
10 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network derives the currents applied on each unselected bit line from the current applied on the selected bit line.
15 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, the switching network comprises a plurality of switches, each switch being coupled between a pair of adjacent bit lines, and each switch operable to couple the bit lines together responsive to a switch control signal being active and to isolate the bit lines responsive to the switch control signal being inactive, and further wherein each switch has resistance when the switch control signal is active, and wherein the value of the resistance is selected to ensure a minimum portion of the current applied on the selected bit line is applied to each unselected bit line adjacent the selected bit line.
15 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- an MRAM memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- array including
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
- and
- a switching network coupled to the bit lines, the switching network operable to apply a column current on at least one unselected bit line, each applied column current being applied in a first direction opposite a second direction of a current applied on a selected bit line, wherein the switching network applies the column current on the at least one unselected bit line adjacent the selected bit line.
15 more elements
Dependencies are inferred from the claim text.