Reference cells with integration capacitor
AssigneeAtmos Corporation
InventorWlodek Kurjanowicz
Life of this patent
Estimating the term…
Abstract
A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalisation between the dummy memory cell having a logic “1” voltage potential and the dummy memory cell having a logic “0” voltage potential. The integration capacitor shares charge with both dummy cell storage capacitors during an equalisation operation to compensate for bitline voltage differences during various access cycle.
Claims18
A DRAM bitline reference circuit including a reference storage capacitor coupled to each bitline of a complementary pair of bitlines, comprising:
- an integration capacitor for sharing charge with the reference storage capacitors;
- a precharge circuit for charging the integration capacitor to a reference voltage level;
- and, an equalization circuit for coupling the integration capacitor to the reference storage capacitors.
A method for equalizing a first reference memory cell storage capacitor and a second reference memory cell storage capacitor coupled to a complementary pair of bitlines comprising:
- a) precharging an integration capacitor, the first reference memory cell storage capacitor and the second reference memory cell storage capacitor to a reference voltage level;
- b) driving the complementary pair of bitlines to complementary voltage levels;
- c) charging the first and second reference memory cell storage capacitors through the complementary pair of bitlines;
- and,
- d) equalizing the first reference memory cell storage capacitor, the second reference memory cell storage capacitor and the integration capacitor to each other.
A DRAM bitline reference circuit comprising:
- a first reference cell having an access transistor and a storage capacitor;
- a second reference cell having an access transistor and a storage capacitor;
- a bitline coupled to the first reference cell;
- a complementary bitline coupled to the second reference cell;
- an integration capacitor;
- a precharge transistor for coupling a reference voltage to the integration capacitor, and, an equalization circuit for coupling the integration capacitor to the storage capacitors of the first and second reference cells.
A DRAM memory comprising:
- a DRAM bitline reference circuit having a reference storage capacitor coupled to each bitline of a complementary pair of bitlines, the bitline reference circuit including
- an integration capacitor for sharing charge with the reference storage capacitors;
- a precharge circuit for charging the integration capacitor to a reference voltage level;
- and,
- an equalization circuit for coupling the integration capacitor to the reference storage capacitors.
Dependencies are inferred from the claim text.