First bit databurst firing of IO equilibrating ending signal based on column access signal

A memory device comprising:

• means for firing an IO equilibrating ending signal based upon a column access signal for a first bit of a data burst of a read command;
• and
• means for firing the IO equilibrating ending signal based upon a clock signal for subsequent bits in the data burst.

A memory device comprising:

• means for firing an IO equilibrating ending signal based upon a column access signal for a first bit of a data burst of a write command;
• and
• means for firing the IO equilibrating ending signal based upon a clock signal for subsequent bits in the data burst.

A synchronous dynamic random access memory (SDRAM) device comprising:

• a circuit, the circuit receiving an IO equilibrating ending signal, wherein the IO equilibrating ending signal is fired based upon a column access signal for a first bit of a data burst, and wherein the IO equilibrating ending signal is fired based upon a clock signal for subsequent bits in the data burst.

A system comprising:

• a microprocessor;
• and
• a memory device in electrical connection to the microprocessor, the memory device receiving from the microprocessor an IO equilibrating ending signal, wherein the IO equilibrating ending signal is fired based upon a column access signal for a first bit of a data burst, and wherein the IO equilibrating ending signal is fired based upon a clock signal for subsequent bits in the data burst.

A system comprising:

• a microprocessor;
• and
• a memory device in electrical connection to the microprocessor, the memory device receiving from the microprocessor an IO equilibrating ending signal, wherein the IO equilibrating ending signal is fired based upon a column access signal for a first bit of a data burst in a read command, and wherein the IO equilibrating ending signal is fired based upon a clock signal for subsequent bits in the data burst.

A system comprising:

• a microprocessor;
• and
• a memory device in electrical connection to the microprocessor, the memory device receiving from the microprocessor an IO equilibrating ending signal, wherein the IO equilibrating ending signal is fired based upon a column access signal for a first bit of a data burst in a write command, and wherein the IO equilibrating ending signal is fired based upon a clock signal for subsequent bits in the data burst.

A memory device in combination with a microprocessor comprising:

• a circuit, the circuit receiving an IO equilibrating ending signal from the microprocessor, wherein the IO equilibrating ending signal is fired based upon a column access signal for a first bit of a data burst, and wherein the IO equilibrating ending signal is fired based upon a clock signal for subsequent bits in the data burst.

A method of firing signals for a memory device, comprising:

• initially firing an IO equilibrating ending signal based upon a column access signal, and subsequently firing the IO equilibrating ending signal based upon a clock signal.

A method for firing an IO equilibrating ending signal based upon various bits of data from a data burst, comprising:

• for a first bit of a data burst, firing an IO equilibrating ending signal based upon a column access signal;
• and
• for one or more subsequent bits of the data burst, firing the IO equilibrating ending signal based upon a clock signal.