Semiconductor device

A semiconductor device, comprising a word line, a first bit line pair, a memory cell provided at an intersection of said word line and said first bit line pair, a second bit line pair, a switch circuit for connecting said first bit line pair and said second bit line pair, a sense amplifier including a first circuit connected to said first bit line pair and a second circuit connected to said second bit line pair, a first precharge circuit for precharging said first bit line pair to a first precharge potential and a second precharge circuit for precharging said second bit line pair to a second precharge potential, wherein

• said second circuit amplifies one of said first and second bit line pairs to a first potential and the other to a second potential from a storage signal of said memory cell,
• said first precharge potential is ranged between said first potential and said second potential,
• said second precharge potential is said second potential,
• said first circuit includes a first MOSFET having a gate connected to one of said first bit line pair and a second MOSFET having a gate connected to the other of said first bit line pair with a source thereof connected to a source of said first MOSFET,
• said second circuit includes P-type third and fourth MOSFETs in which sources are respectively connected in common and gates and drains are cross-connected and N-type fifth and sixth MOSFETs in which sources are respectively connected in common, drains are connected corresponding to the drains of said third and fourth MOSFETs and gates and drains are cross-connected,
• the drains of said first and second MOSFETs are respectively connected to the drains of said fifth and sixth MOSFETS,
• the sources of said first and second MOSFETs are connected to a first control line, and
• the sources of said fifth and sixth MOSFETs are connected to a second control line.

A semiconductor device, comprising a word line, a first bit line pair, a memory cell provided at an intersection of said word line and said first bit line pair, a second bit line pair, a switch circuit for connecting said first bit line pair and said second bit line pair, a sense amplifier including a first circuit connected to said first bit line pair and a second circuit connected to said second bit line pair, a first precharge circuit for precharging said first bit line pair to a first precharge potential and a second precharge circuit for precharging said second bit line pair to a second precharge potential, wherein

• said second circuit amplifies one of said first and second bit line pairs to a first potential and the other to a second potential from a storage signal of said memory cell,
• said first precharge potential is ranged between said first potential and said second potential,
• said second precharge potential is said second potential,
• said first circuit includes a first MOSFET having a gate connected to one of said first bit line pair and a second MOSFET having a gate connected to the other of said first bit line pair with a source thereof connected to a source of said first MOSFET,
• said second circuit includes a latch circuit including a plurality of third MOSFETs,
• said switch circuit includes a fourth MOSFET in which a source/drain route is connected between one of said first bit line pair and one of said second bit line pair and a fifth MOSFET in which a source/drain route is connected between the other of said first bit line pair and the other of said second bit line pair, and
• said fourth and fifth MOSFETs respectively have gate insulation films which are thicker than gate insulation films of said first to third MOSFETs.

A semiconductor device comprising a first word line and a second word line, a first bit line pair including a first bit line and a second bit line, a first memory cell provided at an intersection of said first word line and said first bit line, a second memory cell provided at an intersection of said second word line and said second bit line, a second bit line pair including a third bit line and a fourth bit line, a first switch circuit for connecting said first bit line and said third bit line, a second switch circuit for connecting said second bit line and said fourth bit line and a sense amplifier connected to said second bit line pair, wherein

• said sense amplifier amplifies information stored in said first and second memory cells to a first potential on said third bit line and to a second potential on said fourth bit line,
• said first and second switch circuits isolate, in a first period to read said first or second memory cell, said first bit line pair and second bit line pair, and
• when stored information is read from said first memory cell in a subsequent second period, said sense amplifier writes said first potential to said first bit line under the condition that said first switch circuit connects said first bit line and said third bit line and said second switch circuit isolates said second bit line and said fourth bit line, and when stored information is read from said second memory cell, said sense amplifier writes said second potential to said second bit line under the condition that said second switch circuit connects said second bit line and said fourth bit line and said first switch circuit isolates said first bit line and said third bit line.