Semiconductor memory device capable of switching output data width
AssigneeRenesas Technology Corp.
InventorsYukiko Maruyama, Yasuhiko Tsukikawa, Mikio Asakura, Takashi Itou
Life of this patent
Estimating the term…
Abstract
In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.
Claims4
A semiconductor memory device having first and second multi-bit test modes capable of simultaneously writing test data supplied to a single data input/output pad in a plurality of memory cells, comprising:
- a memory mat including said plurality of memory cells arranged in rows and columns, said memory mat including
- a first pair of bit lines, provided in correspondence to first column of said memory cells, including first and second bit lines transmitting signals complementary to each other,
- a second pair of bit lines, provided in correspondence to second column of said memory cells, including a third bit line adjacent to said second bit line and a fourth bit line transmitting complementary signals with said third bit line,
- a first pair of data lines transmitting data to said first pair of bit lines, and
- a second pair of data lines transmitting data to said second pair of bit lines;
- and
- an input/output circuit zone inputting/outputting data in/from said memory mat, said input/output circuit zone including
- a first transmission circuit transmitting said test data to said first pair of data lines in said first and second multi-bit test modes, and
- a second transmission circuit transmitting said test data to said second pair of data lines with reverse polarity in said first multi-bit test mode and with straight polarity in said second multi-bit test mode.
Dependencies are inferred from the claim text.