Circuit for testing ferroelectric capacitor in FRAM

A circuit for testing a ferroelectric capacitor in an FRAM for storing data in the ferroelectric capacitor, comprising:

• a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor;
• a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal;
• an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal;
• a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal;
• a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit output within a specific period;
• an input drive control part for receiving the reference voltage signal, a voltage signal of the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and providing a drive voltage to a second electrode of the ferroelectric capacitor in response to the test pulse signal;
• a measured result forwarding part for receiving the reference voltage signal, and the voltage signal from the first electrode at a non-inversion terminal, and an inversion terminal thereof respectively, and amplifying, and forwarding a voltage variation between the electrodes of the ferroelectric capacitor;
• and
• a sense capacitor connected between the first electrode of the ferroelectric capacitor, and the measured result forwarding part for sensing voltage variation of the ferroelectric capacitor.

A circuit for testing a ferroelectric capacitor in an FRAM for storing data in the ferroelectric capacitor, comprising:

• a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor;
• a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal;
• an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal;
• a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal;
• a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit output within a specific period;
• an input drive control part for receiving the reference voltage signal, a voltage signal of the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and providing a drive voltage to a second electrode of the ferroelectric capacitor in response to the test pulse signal;
• a measured result forwarding part for receiving the reference voltage signal, and the voltage signal from the first electrode at a non-inversion terminal, and an inversion terminal thereof respectively, and amplifying, and forwarding a voltage variation between the electrodes of the ferroelectric capacitor;
• and
• a sense resistor connected between the non-inversion terminal, and the inversion terminal of the amplification part.