Individual memory page activity timing method and system
AssigneeIntel Corporation
InventorJeffrey R. Wilcox
Life of this patent
Estimating the term…
Abstract
A per bank closure system for use in a multi-bank memory includes a timer, an activity and a closure and closure register. The timer is used to define timing windows. The banks of the memory are mapped to bits in the activity and closure registers. Page activity occurring a timing window is tracked by setting appropriate bit(s) in the activity register and resetting appropriate bit(s) in the closure register. At the end of each timing window, page(s) that were both opened in the previous timing window and are not represented in the activity register are scheduled for closure by setting corresponding bit(s) in the closure register. Then the activity register is reset and the process is repeated.
Claims29
A method for use with a memory having a plurality of banks, the method comprising:
- detecting memory accesses to the memory;
- tracking, for each bank of the plurality of banks, an amount of time that has elapsed for each detected memory access using a number of timers less than the number of banks in the plurality of banks.
An apparatus for use with a memory having a plurality of banks, the apparatus comprising:
- means, couplable to the memory, for detecting memory accesses to each bank of the plurality of banks;
- means for tracking an amount time that has elapsed for each bank of the plurality of banks having a detected memory access using a number of timers that is less than the number of banks in the plurality of banks.
A circuit for use with a memory having a plurality of banks, the circuit comprising:
- a timer to define a plurality of sequential timing windows;
- a first register having a plurality of bits associated with the plurality of banks, wherein each bank of the plurality of banks has an associated bit in the first register;
- a second register having a plurality of bits, each bank of the plurality of banks having an associated bit in the second register;
- and
- a logic circuit coupled to the timer and first and second registers, the logic circuit to track in the first register each bank of the plurality of banks for which a memory access occurred during a first timing window.
A method for use with a memory having a plurality of banks, the method comprising:
- resetting a timer to start a first timing window;
- determining whether the timer has expired;
- if the timer is not expired, detecting a memory access;
- determining a bank addressed by the detected memory request;
- and
- setting a bit in a first register that corresponds to the bank determined to be addressed by the detected memory request.
A system comprising:
- a processor;
- a memory having a plurality of banks;
- a memory controller coupled to the processor and the memory, wherein the memory controller includes:
- a timer to define a plurality of sequential timing windows;
- a first register having a plurality of bits, wherein each bank of the plurality of banks has a corresponding bit in the first register;
- and
- a logic circuit coupled to the timer and first register, the logic circuit to track in the first register each bank of the plurality of banks for which a memory access occurred during a first timing window.
Dependencies are inferred from the claim text.