Semiconductor memory device for providing address access time and data access time at a high speed
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsJe-Hun Ryu, Jong-Hee Han
Life of this patent
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Abstract
A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.
Claims14
A semiconductor memory device comprising:
- a clock control unit for receiving a delay locked loop (DLL) disable signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal to generate a DLL control signal and a clock selection signal;
- a clock generation unit for receiving an external clock and the power-up signal to generate an internal clock;
- a DLL clock buffer unit for generating a DLL clock using the external clock;
- a column address strobe (CAS) buffer unit for receiving and buffering the DLL control signal, an external CAS signal and a reference voltage signal to generate an internal CAS signal and an inverted internal CAS signal;
- and
- a CAS latch unit for receiving and latching the internal CAS signal, the inverted internal CAS signal, the internal clock, the DLL clock, the DLL control signal, the external CAS signal and the reference voltage signal to generate a final CAS signal and an inverted final CAS signal.
Dependencies are inferred from the claim text.