Bus interface circuit and receiver circuit

A receiver circuit receiving data which is output to a bus line, wherein said bus line is precharged to a predetermined precharge voltage during a precharge period before data is output from an output circuit to said bus line, and

• wherein a logic amplitude of a signal output to said bus line is determined by the precharge voltage and a power supply voltage of one of first and second power supplies for driving said output circuit and/or receiver circuit,
• said receiver circuit comprising:
• first and second transistors of second type conductivity, connected in parallel with one of ends thereof tied together to said first power supply, said first transistor controlled to be on and off respectively when the precharge control signal controlling a precharge operation is active and inactive;
• a third transistor of first type conductivity, connected between other ends, which are tied together, of said first and second transistors and said bus line and having a control terminal connected to said precharge power supply terminal;
• a first inverter having an input terminal connected to a common connection node of said first to third transistor and having an output terminal connected to a control terminal of said second transistor;
• a transfer gate having one end connected to the connection node of said first to third transistors and being controlled to be off and on respectively when the precharge control signal is active and inactive;
• and
• a buffer circuit having an input terminal connected to another end of said transfer gate and having an output terminal connected to an output terminal of said receiver circuit.

A receiver circuit precharging a first bus line and receiving data, wherein said first bus line is precharged to a predetermined precharge voltage during a precharge period before data is output from an output circuit to said first bus line, and

• wherein a logic amplitude of a signal output to said first bus line is determined by the precharge voltage and a power supply voltage of one of first and second power supplies driving said output circuit and/or receiver circuit, said receiver circuit comprising:
• a first transistor of first type conductivity, inserted between a precharge power supply voltage terminal which determines the precharge voltage of said first bus line, and said bus line;
• a first inverter having an input terminal for receiving an inverted signal of a precharge control signal for controlling a precharge operation, with the precharge power supply voltage being supplied as a drive power supply voltage, and having an output terminal for outputting a signal at a precharge power supply voltage level to supply the output signal to a gate of said first transistor, when the precharge control signal is active, wherein, when the output signal of said first inverter is at the precharge power supply voltage, said first transistor is turned on to precharge said first bus line;
• second and third transistors of second type conductivity, connected in parallel with one of ends thereof tied together to said first power supply, said second transistor having a control terminal for receiving an inverted signal of the precharge control signal and being controlled to be on and off respectively when the precharge control signal is active and inactive;
• a fourth transistor of first type conductivity, connected between other ends, which are tied together, of said second and third transistors and said bus line, and having a control terminal connected to said precharge power supply terminal;
• a second inverter having an input terminal connected to a common connection node of said second to fourth transistors, said third transistor having a control terminal connected to an output terminal of said second inverter;
• and
• a buffer circuit having an input terminal connected to the output terminal of said second inverter and having an output terminal connected to a second bus line.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a sense amplifier outputting a signal of a logic value corresponding to data of a memory cell selected from said memory cell array;
• a first bus line;
• a first bus line driver circuit receiving the signal output from said sense amplifier and driving the first bus line when the output signal of said sense amplifier is one of a first and second logic values;
• a first precharge circuit, receiving a first precharge control signal activated every read cycle of said first bus line and precharging said first bus line to a first precharge voltage when the first precharge control signal is activated to indicate a precharge operation;
• and
• a first receiver circuit holding a signal output to said first bus line in a preceding read cycle when said first precharge control signal is active and for receiving a signal from said first bus line to convert a level of the received signal for output as an output signal when the first precharge control signal is inactive.