Temperature-compensated output buffer circuit

An output buffer circuit, comprising:

• a first output buffer stage for providing an output signal indicative of a logic of a data signal;
• and
• at least one second output buffer stage selectively activated in response to a temperature-dependent control signal;
• wherein each second output buffer stage is adapted to provide an output signal indicative of the logic of the data signal in parallel with the output signal of the first output buffer stage when activated;
• and
• wherein each second output buffer stage is adapted to present a high-impedance state when deactivated.

An output buffer circuit, comprising:

• an output driver for providing two control signals representative of a data signal;
• a first output buffer stage for providing an output signal indicative of the data signal in response to the two output driver control signals;
• at least one switch responsive to a temperature-dependent control signal, wherein each switch is adapted to pass the two output driver control signals when the temperature-dependent control signal has a first logic value and to pass two complementary control signals when the temperature-dependent control signal has a second logic value;
• at least one second output buffer stage in parallel with the first output buffer stage, each second output buffer stage coupled to one of the switches in a one-to-one relationship for receiving its output control signals, wherein each second output buffer stage is adapted to provide an output signal indicative of the data signal when the temperature-dependent control signal has the first logic value and to present a high-impedance state when the temperature-dependent control signal has the second logic value.

An output buffer circuit, comprising:

• an output driver for providing two control signals representative of a data signal;
• a first output buffer stage for providing an output signal indicative of the data signal in response to the two output driver control signals;
• at least one switch responsive to a temperature-dependent control signal, wherein each switch is adapted to pass the two output driver control signals when the temperature-dependent control signal has a first logic value and to pass two complementary control signals when the temperature-dependent control signal has a second logic value;
• at least one second output buffer stage in parallel with the first output buffer stage, each second output buffer stage coupled to one of the switches in a one-to-one relationship for receiving its output control signals, wherein each second output buffer stage is adapted to provide an output signal indicative of the data signal when the temperature-dependent control signal has the first logic value and to present a high-impedance state when the temperature-dependent control signal has the second logic value;
• a temperature-dependent voltage generator for generating the temperature-dependent voltage signal as a function of an ambient temperature;
• a comparator having a first input for receiving a reference voltage and a second input for receiving the temperature-dependent voltage signal, wherein the comparator is adapted for generating the temperature-dependent control signal having the first logic level when the temperature-dependent voltage signal is indicative of an ambient temperature at or above a predetermined threshold and having the second logic level when the temperature-dependent voltage signal is indicative of an ambient temperature below the predetermined threshold.

A method of providing a data output signal, comprising:

• generating a first output signal at a first output buffer stage in response to a data signal;
• selectively activating a second output buffer stage to generate a second output signal in response to the data signal when an ambient temperature is greater than or equal to a predetermined threshold;
• and
• adding the first output signal and the second output signal to generate the data output signal.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer includes at least one output buffer circuit, comprising:
• a first output buffer stage for providing an output signal indicative of a logic of a data signal to one of the data lines, wherein the data signal is indicative of a data value of one of the memory cells;
• at least one second output buffer stage, wherein each second output buffer stage is adapted to selectively generate, in response to a temperature-dependent control signal, an output signal indicative of the logic of the data signal for providing to the same data line as the output signal of the first output buffer stage.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer includes at least one output buffer circuit, comprising:
• a first output buffer stage for providing an output signal indicative of a logic of a data signal to a first one of the, data lines;
• and
• at least one second output buffer stage selectively activated in response to a temperature-dependent control signal;
• wherein each second output buffer stage is adapted to provide an output signal indicative of the logic of the data signal to the first one of the data lines when activated;
• and
• wherein each second output buffer stage is adapted to present a high-impedance state to the first one of the data lines when deactivated.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer includes at least one output buffer circuit, comprising:
• an output driver for providing two control signals representative of a data value of a memory cell;
• a first output buffer stage for providing an output signal on a first one of the data lines, wherein the output signal is indicative of the data value of the memory cell;
• at least one switch responsive to a temperature-dependent control signal, wherein each switch is adapted to pass the two output driver control signals when the temperature-dependent control signal has a first logic value and to pass two complementary control signals when the temperature-dependent control signal has a second logic value;
• at least one second output buffer stage having an output coupled to the first one of the data lines, each second output buffer stage coupled to one of the switches in a one-to-one relationship for receiving its output control signals, wherein each second output buffer stage is adapted to provide an output signal on its output indicative of the data value of the memory cell when the temperature-dependent control signal has the first logic value and to present a high-impedance state on its output when the temperature-dependent control signal has the second logic value.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer includes at least one output buffer circuit, comprising:
• an output driver for providing two control signals representative of a data value of a memory cell;
• a first output buffer stage for providing an output signal to a first one of the data lines in response to the two output driver control signals, wherein the output signal is indicative of the data value of the memory cell;
• at least one switch responsive to a temperature-dependent control signal, wherein each switch is adapted to pass the two output driver control signals when the temperature-dependent control signal has a first logic value and to pass two complementary control signals when the temperature-dependent control signal has a second logic value;
• at least one second output buffer stage, each second output buffer stage having an output coupled to the first one of the data lines and an input coupled to receive the output control signals of one of the switches, wherein each second output buffer stage is adapted to provide an output signal to the first one of the data lines that is indicative of the data value of the memory cell when the temperature-dependent control signal has the first logic value and to present a high-impedance state to the first one of the data lines when the temperature-dependent control signal has the second logic value;
• a temperature-dependent voltage generator for generating the temperature-dependent voltage signal as a function of an ambient temperature;
• a comparator having a first input for receiving a reference voltage and a second input for receiving the temperature-dependent voltage signal, wherein the comparator is adapted for generating the temperature-dependent control signal having the first logic level when the temperature-dependent voltage signal is indicative of an ambient temperature above a predetermined threshold and having the second logic level when the temperature-dependent voltage signal is indicative of an ambient temperature below the predetermined threshold.