Semiconductor memory arrangement
AssigneeInfineon Technologies AG
InventorEsther Vega Ordonez
Life of this patent
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Abstract
To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks (9) that each memory block (9) has a corresponding data bus and a group of sense amplifiers (1) connected to this data bus (2) associated with it. In this way it is possible for the bus-line capacitance (CB), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector (6).
Claims8
Semiconductor memory arrangement having a plurality of memory sectors, the storage locations in each memory sector being connectable to a global bit line via a local bit line, and having a plurality of sense amplifiers, each sense amplifier being connectable via a data bit to one of the global bit lines, wherein the sense amplifiers are combined into a plurality of groups of sense amplifiers, the sense amplifiers in each group being connectable to a corresponding global bit line via a data bus associated with the given group, wherein the data bus number i is a data bus comprising mi bits and the group of sense amplifiers associated with data bus number i comprises mi sense amplifiers, the individual data buses and the individual groups of sense amplifiers being so designed, to allow a total of N bits to be read out from the semiconductor memory arrangement, that ∑ i = 1 n m i = N
- is true, where n is the number of data buses, i.e. the number of groups of sense amplifiers.
Semiconductor memory arrangement having a plurality of memory sectors, the storage locations in each memory sector being connectable to a global bit line via a local bit line, and having a plurality of sense amplifiers, each sense amplifier being connectable via a data bus to one of the global bit lines, wherein the sense amplifiers are combined into a plurality of groups of sense amplifiers, the sense amplifiers in each group being connectable to a corresponding global bit line via a data lines associated with the given group, wherein the individual memory sectors in the semiconductor memory arrangement are arranged in rows and columns in a matrix, and the memory sectors a column of the semiconductor matrix arrangement are connected together by at least one global bit line.
Dependencies are inferred from the claim text.