Sensing scheme for low-voltage flash memory

A sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to the floating-gate memory cell, the sensing device comprising:

• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a field-effect transistor coupled between a second potential node and the input node of the sensing device, the field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• and
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device;
• wherein the third potential node is coupled to receive a third potential;
• and
• wherein the fourth potential node is coupled to receive a fourth potential.

A sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to the floating-gate memory cell, the sensing device comprising:

• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a p-channel field-effect transistor coupled between a second potential node and the input node of the sensing device, the p-channel field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device, wherein the third potential node is coupled to receive a third potential and the fourth potential node is coupled to receive a fourth potential;
• and
• a reference current control signal generator having a diode coupled between a fifth potential node and the gate of the p-channel field-effect transistor of the reference current path, the reference current control signal generator further having a resistive component coupled between a sixth potential node and the output node of the reference current control signal generator, wherein the fifth potential node is coupled to receive a fifth potential and the sixth potential node is coupled to receive a sixth potential.

A sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to the floating-gate memory cell, the sensing device comprising:

• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a p-channel field-effect transistor coupled between a second potential node and the input node of the sensing device, the p-channel field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device, wherein the third potential node is coupled to receive a third potential and the fourth potential node is coupled to receive a fourth potential;
• and
• a reference current control signal generator having an output node coupled to the gate of the p-channel field-effect transistor of the reference current path for providing the reference current control signal, the reference current control signal generator comprising:
• a plurality of diode-connected p-channel field-effect transistors, each diode-connected p-channel field-effect transistor having a first source/drain region coupled to receive a fifth potential from a fifth potential node, a second source/drain region coupled to the output node of the reference current control signal generator, and a gate coupled to output node of the reference current control signal generator, wherein each p-channel field-effect transistor of the plurality of diode-connected p-channel field-effect transistors is sized to be substantially identical to the p-channel field-effect transistor of the reference current path;
• a first n-channel field-effect transistor having a first source/drain region coupled to the output node of the reference current control signal generator, a second source/drain region, and a gate coupled to receive a first control signal, wherein the first n-channel field-effect transistor is sized to be substantially identical to a first pass transistor coupled between the floating-gate memory cell and the sensing device;
• a second n-channel field-effect transistor having a first source/drain region coupled to the second source/drain region of the first field-effect transistor, a second source/drain region, and a gate coupled to receive the first control signal, wherein the second n-channel field-effect transistor is sized to be substantially identical to a second pass transistor coupled between the floating-gate memory cell and the sensing device;
• and
• a resistive component having an input coupled to the second source/drain region of the second field-effect transistor and an output coupled to receive a sixth potential from a sixth potential node, the resistive component including a first resistive element coupled between the second source/drain region of the second field-effect transistor and the sixth potential node and a third n-channel field-effect transistor coupled between the first resistive element and the sixth potential node, the third n-channel field effect transistor having a gate coupled to receive the first control signal;
• wherein the third potential and the fifth potential are the same potential and that potential is a supply potential;
• and
• wherein the fourth potential and the sixth potential are the same potential and that potential is a ground potential.

A flash memory device, comprising:

• an array of floating-gate memory cells;
• and
• a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells, the sensing device further comprising:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path coupled between a second potential node and the input node of the sensing device, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• and
• a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal responsive to a potential level of the input node of the sensing device relative to a threshold point, wherein the output signal is indicative of the programmed state of the floating-gate memory cell.

A flash memory device, comprising:

• an array of floating-gate memory cells;
• and
• a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells, the sensing device further comprising:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a field-effect transistor coupled between a second potential node and the input node of the sensing device, the field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• and
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device;
• wherein the third potential node is coupled to receive a third potential;
• and
• wherein the fourth potential node is coupled to receive a fourth potential.

A flash memory device, comprising:

• an array of floating-gate memory cells;
• and
• a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells, the sensing device further comprising:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a p-channel field-effect transistor coupled between a second potential node and the input node of the sensing device, the p-channel field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device, wherein the third potential node is coupled to receive a third potential and the fourth potential node is coupled to receive a fourth potential;
• and
• a reference current control signal generator having a diode coupled between a fifth potential node and the gate of the p-channel field-effect transistor of the reference current path, the reference current control signal generator further having a resistive component coupled between a sixth potential node and the output node of the reference current control signal generator, wherein the fifth potential node is coupled to receive a fifth potential and the sixth potential node is coupled to receive a sixth potential.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device has an array of floating-gate memory cells and a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells and further comprises:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path coupled between a second potential node and the input node of the sensing device, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• and
• a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal responsive to a potential level of the input node of the sensing device relative to a threshold point, wherein the output signal is indicative of the programmed state of the floating-gate memory cell.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device has an array of floating-gate memory cells and a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells and further comprises:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a field-effect transistor coupled between a second potential node and the input node of the sensing device, the field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• and
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device;
• wherein the third potential node is coupled to receive a third potential;
• and
• wherein the fourth potential node is coupled to receive a fourth potential.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device has an array of floating-gate memory cells and a single-ended sensing device for sensing a programmed state of a floating-gate memory cell of the array of floating-gate memory cells, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell of the array of floating-gate memory cells and further comprises:
• a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;
• a reference current path having a p-channel field-effect transistor coupled between a second potential node and the input node of the sensing device, the p-channel field-effect transistor having a gate coupled to receive a reference current control signal, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device;
• a sense inverter having a p-channel stage coupled between a third potential node and an output of the sense inverter, the p-channel stage comprising at least one p-channel field-effect transistor each having a gate coupled to the input node of the sensing device, the sense inverter further having an n-channel stage coupled between a fourth potential node and the output of the sense inverter, the n-channel stage comprising at least one n-channel field-effect transistor each having a gate coupled to the input node of the sensing device, wherein the third potential node is coupled to receive a third potential and the fourth potential node is coupled to receive a fourth potential;
• and
• a reference current control signal generator having a diode coupled between a fifth potential node and the gate of the p-channel field-effect transistor of the reference current path, the reference current control signal generator further having a resistive component coupled between a sixth potential node and the output node of the reference current control signal generator, wherein the fifth potential node is coupled to receive a fifth potential and the sixth potential node is coupled to receive a sixth potential.