Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor

A circuit for programming a plurality of memory cells connected, through column decode means, to a program voltage reference provided by a charge pump circuit, and connected to a second voltage reference, with the cell gate terminals sharing connection to a word line, the circuit comprising:

• an operational amplifier having at least one input terminal connected to an external voltage reference and an output terminal connected, through suitable row decode means, to said word line in order to provide a word voltage signal, said operational amplifier connected with said cells in a program loop arranged to adjust the slope of an output voltage ramp from said charge pump circuit to suit the demand from said cells.

A method for programming a plurality of memory cells connected in parallel between first and second supply references and having their gate terminals connected together and also connected through a decoder to an output terminal of an operational amplifier configured to generate a word voltage signal, the method comprising:

• forming a program loop that includes the cells to be programmed, the operational amplifier, and a charge pump circuit;
• and
• generating a voltage from the charge pump circuit, the voltage having a voltage ramp with a slope that is a function of a voltage demand from the cells to be programmed.

A circuit for programming a plurality of memory cells connected through a column decoder to a program voltage reference provided by a charge pump circuit and further connected to a second voltage reference, the plurality of memory cells having gate terminals sharing a connection to a word line, the circuit comprising:

• an operational amplifier having at least one input terminal connected to an external voltage reference and an output terminal connected through a row decoder to the word line to provide a word voltage signal, the operational amplifier connected with the plurality of memory cells in a program loop arranged to adjust the slope of an output voltage ramp from the charge pump circuit to meet the demand from the plurality of memory cells to be programmed;
• and
• a limiter circuit connected between the charge pump circuit and the program voltage reference, the limiter circuit comprising a transistor connected between the charge pump circuit and the program voltage reference, and an additional operational amplifier having a first input terminal connected to the program voltage reference, a second input terminal connected to a second fixed external voltage reference, and an output terminal connected to a gate terminal of the transistor.

A circuit for programming a plurality of memory cells connected through a column decoder to a program voltage reference provided by a charge pump circuit, and further connected to a second voltage reference, the plurality of memory cells having cell gate terminals sharing a connection to a word line, the circuit comprising:

• an operational amplifier having at least one input terminal connected to an external voltage reference and an output terminal connected through a row decoder to the word line to provide a voltage signal, the operational amplifier connected to the plurality of memory cells in a program loop arranged to adjust the slope of an output voltage from the charge pump circuit to meet the demand from the plurality of memory cells, the operational amplifier comprising an integrator type operational amplifier having an input terminal arranged to receive the charge pump voltage signal and connected through first and second cascaded amplifiers to a control terminal of a transistor that in turn is connected between the program voltage reference and an output terminal of the operational amplifier.