Gapless programming for a NAND type flash memory
AssigneeFujitsu Limited
InventorMasaru Yano
Life of this patent
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Abstract
Techniques, including a system and method, for reducing the total time for writing a plurality of pages to a NAND-type flash memory array are provided. In one embodiment, the writing is divided into two parts. The first part receives and holds the next page in an intermediate buffer, while the present page, stored in the page buffer, is used to program the memory array. Then the next page is loaded into the page buffer. In parallel with the next page being programmed into the memory array, another page is input and held in the intermediate buffer. Thus, substantially gapless writing of the plurality of pages to the NAND-type flash memory array is achieved with the associated reduction in total time.
Claims30
A method for writing a plurality of pages to a flash memory using pipelining, said method comprising:
- receiving a first data input comprising a first page;
- and
- programming said first page in parallel with receiving a second data input, said second data input comprising a second page.
A method for substantially gapless programming of a NAND type flash memory, comprising:
- receiving a first data input, comprising a first page;
- programming said first page into a plurality of memory cells of said NAND type flash memory;
- and
- after said receiving said first data input, receiving a second data input in parallel with said programming said first page, wherein said second data input comprises a second page.
A system for improving performance in a NAND type flash memory array, comprising:
- a first buffer circuit for receiving a first data item;
- a memory cell in said NAND type flash memory array that is programmed using said first data item;
- a second buffer circuit for receiving a second data item while said memory cell is programmed using said first data item;
- and
- a switch for transferring said second data item to said first buffer circuit.
A system for improving performance in a NAND type flash memory array, comprising:
- a data latch for receiving a first page data item from a I/O register;
- a dataload switch for transferring said first page data item to a pagebuffer;
- and
- a memory array cell for non-volatile storing of said first page data item, wherein said data latch receives a second page data item in parallel with said storing of said first page data item.
A method for reducing a total time for writing a plurality of sequential pages of data, comprising:
- loading a data latch with a next page of said plurality of sequential pages of data;
- and
- concurrently with said loading, performing operations on a memory array comprising:
- programming said memory array with a page of said plurality of sequential pages of data, said page stored in a pagebuffer;
- verifying said programming by examining a status register;
- and
- when said next page is loaded properly, loading said pagebuffer with said next page.
A method for transferring a plurality of pages to and from a flash memory comprising:
- receiving a first data input comprising a first page;
- programming said first page into said flash memory in parallel with receiving a second data input, said second data input comprising a second page;
- and
- reading a third page from said flash memory in parallel with said programming said first page.
A system for improving performance in a NAND type flash memory array, comprising:
- a first buffer circuit for receiving a first data item;
- a first memory cell in said NAND type flash memory array that is programmed using said first data item;
- a second buffer circuit for receiving a second data item while said first memory cell is programmed using said first data item;
- a switch for transferring said second data item to said first buffer circuit;
- and
- a third buffer circuit for receiving the reading of a second memory cell in said NAND type flash memory array, while said first memory cell is programmed using said first data item.
Dependencies are inferred from the claim text.