Circuits and methods for identifying a defective memory cell via first, second and third wordline voltages

Abstract

Disclosed are circuits and methods of identifying defective memory cells among rows and columns of memory cells. In one embodiment, all the memory cells in an array are programmed to conduct with a conventional read voltage applied and not to conduct with a conventional read-inhibit voltage applied. Any rows that conduct with the read-inhibit voltage applied are termed “leaky,” and are defective. Another read-inhibit voltage lower than the conventional level is selected to cause even leaky cells not to conduct. This test read-inhibit voltage is consecutively applied to each row under test. If one of the rows includes a leaky bit, that bit will conduct with the conventional read-inhibit voltage applied but will not conduct with the test read-inhibit voltage applied. The test flow therefore identifies a row as including a leaky bit when a leak is suppressed by application of the test read-inhibit voltage. A redundant row can be provided to replace a row having a leaky bit.

Dependencies are inferred from the claim text.