Highly-integrated flash memory and mask ROM array architecture
AssigneeAplus Flash Technology, Inc.
InventorsPeter W. Lee, Fu-Chang Hsu
Life of this patent
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Abstract
A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.
Claims36
A memory cell device comprising:
- a first transistor having gate, drain, and source;
- and
- a second transistor having gate, drain, and source, wherein said first transistor drain is coupled to an array bit line, wherein said second transistor source is coupled to an array source line, wherein said first transistor source is coupled to said second transistor drain, wherein said first transistor and said second transistor comprise one Flash transistor and one mask ROM transistor, and wherein the programmed state of said mask ROM transistor can be read.
A memory cell device comprising:
- a first Flash transistor having control gate, flash gate, drain, and source;
- and
- a second Flash transistor having control gate, flash gate, drain, and source, wherein said first Flash transistor drain is coupled to an array bit line, wherein said second Flash transistor source is coupled to an array source line, wherein said first Flash transistor source is coupled to said second Flash transistor drain, wherein said first Flash transistor can turn OFF bit line current in said memory cell device when said second Flash transistor is over-erased and wherein said second Flash transistor can turn OFF bit line current in said memory cell device when said first Flash transistor is over erased.
A device comprising:
- a memory array comprising a plurality of memory cell devices, said memory cell devices comprising:
- a first transistor having gate, drain, and source;
- and
- a second transistor having gate, drain, and source, wherein said first transistor drain is coupled to an array bit line, wherein said second transistor source is coupled to an array source line, wherein said first transistor source is coupled to said second transistor drain, wherein said first transistor and said second transistor comprise one Flash transistor and one mask RON transistor, and wherein the programmed state of said mask RON transistor can be read;
- and
- an access controller capable of accessing said memory array.
A device comprising:
- a memory array comprising a plurality of memory cell devices, said memory cell devices comprising:
- a first transistor having gate, drain, and source;
- and
- a second transistor having gate, drain, and source, wherein said first transistor drain is coupled to an array bit line, wherein said second transistor source is coupled to an array source line, wherein said first transistor source is coupled to said second transistor drain, wherein said first transistor and said second transistor comprise one of the group consisting of:
- one Flash transistor and one mask RON transistor, two Flash transistors, and two mask ROM transistors, and wherein the programmed state of said mask ROM transistor can be read;
- and
- an access controller capable of accessing said memory array.
Dependencies are inferred from the claim text.