Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorTakashi Ohsawa
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Abstract
A semiconductor memory device has MIS transistors to constitute a memory cell array. Each of the MIS transistors has a silicon layer in a floating state. Furthermore, the MIS transistor has a second gate, a potential of which is fixed in order to control a potential of the silicon layer by a capacitive coupling, in addition to a first gate, which forms a channel between a source region and a drain region of the MIS transistor. The MIS transistor dynamically stores a first data state in which the silicon layer has a first potential set by impact ionization generated near a drain junction and a second data state in which the silicon layer has a second potential set by a forward current flowing through the drain junction.
Claims19
A semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising:
- a semiconductor layer;
- a source region formed in the semiconductor layer;
- a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a body region in a floating state;
- a first gate which forms a channel in the body region;
- and
- a second gate formed in addition to the first gate, a potential of the second gate being fixed so as to control a potential of the body region by a capacitive coupling;
- wherein the MIS transistor has a first data state in which the body region has a first potential and a second data state in which the body region has a second potential.
Dependencies are inferred from the claim text.