US 6,687,151 B2Granted

Voltage generation circuit for selectively generating high and negative voltages on one node

AssigneeFujitsu Limited

InventorsToru Endo, Shoichiro Kawashima

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Abstract

An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.

Claims19

Dependent claims

A voltage generation circuit for selectively generating a low voltage lower than a first power supply voltage and a high voltage higher than a second power supply voltage on an output node on the basis of the first and second power supply voltages, the second power supply voltage being higher than the first power supply voltage, the voltage generation circuit comprising:

a first PMOS transistor, having a current path and a control gate, a first end of the current path being connected to the output node, a back gate thereof being connected to a second end of the current path;
a first NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the first PMOS transistor, a second end of the current path thereof being connected to the first power supply voltage;
a first capacitor, having first and second electrodes, the first electrode being connected to the output node;
a second PMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the output node, a back gate thereof being connected to a second end of the current path thereof, the control gate thereof being connected to the first power supply voltage;
a second NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the second PMOS transistor;
and
a control circuit configured to:
raise the second electrode of the first capacitor to the second power supply voltage to step up the output node to the high voltage from a first state where the first and second NMOS transistors are OFF and where the output node and the second electrode of the first capacitor are at the second and first power supply voltages, respectively;
and
lower the second electrode of the first capacitor to the first power supply voltage to step down the output node to the low voltage from a second state where the first and second NMOS transistors are OFF, where a voltage between the control gate and the second end of the current path of each of the first and second PMOS transistors is equal to an absolute value of a threshold voltage thereof, and where the output node and the second electrode of the first capacitor are at the first and second power supply voltages, respectively.

7 more elements

a first PMOS transistor, having a current path and a control gate, a first end of the current path being connected to the output node, a back gate thereof being connected to a second end of the current path;
a second PMOS transistor, having a current path and a control gate, the control gate thereof being connected to the control gate of the first PMOS transistor, a first end of the current path thereof being connected to the second end of the current path of the first PMOS transistor, a back gate thereof being connected to the second power supply voltage;
a first capacitor, having first and second electrodes, the first electrode being connected to the output node;
and
a control circuit configured to:
raise the second electrode of the first capacitor to the second power supply voltage to step up the output node to the high voltage in a first state where the first and second PMOS transistors are OFF and where the output node and the second electrode of the first capacitor are at the second and first power supply voltages, respectively;
and
lower the second electrode of the first capacitor to the first power supply voltage to step down the output node to the low voltage in a second state where the first and second PMOS transistors are OFF and where the output node and the second electrode of the first capacitor are at the first and second power supply voltages, respectively.

5 more elements

Dependencies are inferred from the claim text.