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US 6,687,150 B1Granted
Reference voltage generation for memory circuits
AssigneesInfineon Technologies AG, Kabushiki Kaisha Toshiba
InventorsHans-Oliver Joachim, Takashima Daisaburo
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Abstract
An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.
Claims27
An integrated circuit comprising:
- a memory block having a plurality of memory cells;
- wordlines coupling memory cells in a second direction;
- bitlines coupling memory cells in a first direction;
- a plurality of reference cells, wherein a bitline includes a reference memory cell;
- and
- the bitlines of the memory block are divided into groups of bitlines, wherein at least some of the reference cells within a group are interconnected to average out the reference cell charge variations.
3 more elements
A method for improved generation of reference signal in integrated circuits comprising:
- providing a memory block having a plurality of memory cells coupled in a first direction by wordlines and coupled in a second direction by bitlines;
- providing a plurality of reference memory cells in the memory block, wherein a bitline includes a reference memory cell;
- and
- dividing the bitlines of the memory block into groups of bitlines, wherein at least some of the reference cells within a group are interconnected to average out the reference cell charge variations.
1 more element
Dependencies are inferred from the claim text.