High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
AssigneeUniram Technology Inc.
InventorJeng-Jye Shau
Life of this patent
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Abstract
A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.
Claims31
A method for manufacturing a DRAM (dynamic random access memory) cell array which includes a plurality of memory cells, each having a select-transistor comprising:
- forming a select-transistor-gate for said select-transistor wherein said select-transistor-gate having substantially a same thickness as a typical transistor of a logic circuit;
- and
- applying implant processes in forming said select-transistor wherein said select-transistor having substantially a same threshold voltage as said typical transistor of a logic circuit.
A method for manufacturing a memory cell array on a substrate comprising:
- forming transistors on said substrate wherein each transistor functioning as select transistor for a memory cell of said memory cell array wherein each select transistor having a gate covered by an insulation protective layer wherein said insulation protective layer disposed next to a field oxide layer defining open areas therein-between;
- forming trench capacitors for said memory cells by etching said open areas with edges of said trenches defined by said insulation protective layer and said field oxide layer.
A method for manufacturing a memory cell array on a substrate comprising:
- forming a plurality of select transistors on said substrate having polysilicon gates covered by an insulation protective layer;
- connecting said gate of a plurality of said logic transistors to a ground voltage thus defining a plurality of isolation transistors each separating two adjacent select transistors wherein said insulation protective layer of said isolation transistors and said adjacent logic transistors defining open areas therein-between;
- forming trench capacitors for said memory cells by etching said open areas with edges of said trenches defined by said insulation protective layer of said isolation transistors and said adjacent logic transistors.
A memory cell array supported on a substrate comprising:
- a plurality of memory cells each having a select-transistor wherein each of said select-transistor having a select-transistor-gate;
- said select-transistor-gate having substantially a same thickness as a typical transistor of a logic circuit;
- and
- said select-transistor for each of said memory cells having a select-transistor threshold voltage wherein said select-transistor threshold voltage is substantially the same as typical transistor of a logic circuit.
Dependencies are inferred from the claim text.