US 6,686,969 B1Granted

Display device

AssigneeNEC-Mitsubishi Electric Visual Systems Corporation

InventorsKouichirou Hara, Yasuo Murakami

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Abstract

An object is to eliminate the effect of jitter in a sampling clock to realize proper sampling of a video signal. An A/D converter (1) samples a video signal in synchronization with a sampling clock (VCLK) at a rate of a period which is ½ times the video period. The phase of the sampling clock (VCLK) is corrected in a phase correcting circuit (9). The sampled signals are held alternately as data (DL) and (DR) in two latches (14) (15). A data switching portion (16) selects output signals from one of the two latches (14) and (15). A calculating portion (21) calculates an absolute difference value (ΔD) between the data (DL) and (DR) in each video period. A calculating portion (22) calculates a maximum value (Dmax) among the absolute difference values (ΔD) in one frame. A phrase control portion (19) controls the phase correcting circuit (9) and the data switching portion (16) so that a video signal processing circuit (2) can receive sampled signals which are sampled signals which are sampled at a phase corresponding to the center of a rising transition which the maximum value (Dmax) makes as the phase varies.

Claims8

Dependent claims

An apparatus which samples video signals at a calculated phase and provides the sampled signal to a display device, comprising:

a sampling portion for sampling a video signal at a rate of a half period which is ½ times a video period of the video signal;
a selecting portion for outputting as a display signal every other sampled signal which is the video signal sampled at the rate of said half period;
a phase adjusting portion for adjusting the phase of the sampling performed by said sampling portion within a given variable-phase range;
an absolute difference value calculating portion for calculating an absolute difference value which is, when said sampled signals are numbered with respect to one of said sampled signals in order of sampling time, the absolute value of a difference between an odd-numbered sampled signal and the next even-numbered sampled signal;
a maximum absolute difference value calculating portion operatively connected to said absolute difference value calculating portion for calculating a maximum absolute difference value which is a maximum value in a plurality of said absolute difference values;
a phase control portion operatively connected to said maximum absolute difference value calculating portion for controlling said phase adjusting portion under the restriction of said variable-phase range so that said display signal comprises the sampled signals sampled at a phase which is the closest to a phase set at or near the center of a rising transition in which said maximum absolute difference value increases as said phase delays;
and
a video signal processing circuit for processing the display signal and outputting the processed display signal to a display screen.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/645,435Filed 25 Aug 2000
Priority: JP P2000-0567152 Mar 2000
Granted: 3 Feb 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03L 7/091
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
G09G 5/008
Details of the interface to the display terminal: clock recovery
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used