Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer

A translation look-aside buffer circuit for optimizing the translation of virtual addresses into physical addresses using a pipeline implementation, the circuit comprising:

• a translation look-aside buffer cache into which an access is made in a first clock cycle, the translation look-aside buffer cache comprising a plurality of translation look-aside buffer entries operable to buffer information for translating between a virtual address and a physical address;
• and
• a least recently used pointer circuit coupled to the translation look-aside buffer cache, the least recently used pointer circuit operable to generate and store a least recently used pointer, said least recently used pointer configured to point to a translation look-aside buffer entry buffering information least recently used for translation, the least recently used pointer circuit operable to be updated in a second clock cycle to reflect the access into the translation look-aside buffer cache in the first clock cycle, said least recently used pointer comprising a plurality of pointer entries, each of said plurality of pointer entries operable to store status information for said plurality of translation look-aside buffer entries of said look-aside buffer cache, said plurality of pointer entries operable to be updated in said second clock cycle to reflect said access into said translation look-aside buffer cache.

A translation look-aside buffer circuit for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART), the circuit comprising:

• a translation look-aside buffer cache comprising a plurality of translation look-aside buffer entries operable to buffer information, wherein an access is made to the translation look-aside buffer cache for translating between a virtual address and a physical address;
• and
• a least recently used pointer circuit coupled to the translation look-aside buffer cache, the least recently used pointer circuit comprising a plurality of pointer entries, said least recently used pointer circuit operable to store said plurality of pointer entries, each pointer entry operable to point to a respective translation look-aside buffer entry, the plurality of pointer entries ordered according to a degree of usage of the information buffered in each of the translation look-aside buffer entries, wherein an update is made to the least recently used pointer circuit for the access into translation look-aside buffer cache to reflect said access into said translation look-aside buffer cache, and wherein the update to the least recently used pointer circuit is pipelined with the access into translation look-aside buffer cache.