Image display apparatus and method

#The present invention relates to an image display apparatus and method such as a monitor or a data projector having a matrix display device (hereinafter referred to as a display panel) such as a liquid crystal display panel, a digital micromirror device (DMD), a field emission display (FED), a plasma display panel (PDP), or an LED panel. More specifically, the present invention relates to an image display apparatus and method that displays a scaled-up image if an image size of an input image signal is smaller than a size of an effective display area of the display panel.

#FIG. 7 is a diagram showing configuration of a prior art image display apparatus, which is disclosed in Japanese Patent Kokai Publication No. 10-334227 published on Dec. 18, 1998. In the image display apparatus 100 shown in FIG. 7, an image signal is supplied from a terminal 101, and a dot clock SCLK for the image signal is supplied from a terminal 102. The image signal supplied from the terminal 101 is input to a control unit 103 and a time-base converter 104. The dot clock SCLK supplied from the terminal 102 is input to the time-base converter 104. The control unit 103 outputs an output clock DCLK so that a scaled-up image is generated at a frame rate matching a rate at which the input image signal is received. The clock DCLK output by the control unit 103 is supplied to the time-base converter 104, an interpolation circuit 105, and a panel controller 106. Then, the control unit 103 outputs a buffer control signal BANK for controlling a line buffer in the time-base converter 104. The buffer control signal BANK output by the control unit 103 is supplied to the time-base converter 104. Moreover, the control unit 103 outputs a modifier signal Q for determining pixel data used for interpolation and a phase value signal PHASE for determining an interpolation coefficient. The modifier signal Q output from the control unit 103 is input to the time-base converter 104 and the interpolation circuit 105, and the phase value signal PHASE is supplied to the interpolation circuit 105.

#The time-base converter 104 receives the pixel data for the input image in synchronization with the dot clock SCLK, and outputs the received pixel data in synchronization with the output clock DCLK on a different time base according to the buffer control signal BANK supplied from the control unit 103. The pixel data output from the time-base converter 104 is image data scaled up by copying (or repeating) the pixel data. The scaled-up pixel data output from the time-base converter 104 is supplied to the interpolation circuit 105. The interpolation circuit 105 performs predetermined interpolation of the pixel data of the scaled-up image, according to the modifier signal Q and the phase value signal PHASE, and outputs the results of interpolation. The pixel data of the scaled-up image subjected to interpolation and output by the interpolation circuit 105 is supplied to the panel controller 106. The panel controller 106 outputs the scaled-up image subjected to interpolation to the display panel 107 in a signal format compatible with the input interface of the display panel 107. The display panel 107 therefore displays the scaled-up image subjected to interpolation according to the output of the panel controller 106.

#The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

#FIG. 1 is a block diagram showing configuration of an image display apparatus according to a first embodiment of the present invention;

#FIG. 2 is a block diagram showing configuration of a synchronizing signal processing circuit shown in FIG. 1;

#Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications will become apparent to those skilled in the art from the detailed description.

#FIG. 1 is a block diagram showing configuration of an image display apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the image display apparatus of the first embodiment comprises terminals 1, 2, and 3, an input signal measurement circuit 4, a synchronizing signal processing circuit 5, a controller 6, an image decimation circuit 7, a driving circuit 8, an image scale-up circuit 9, and a display panel 10. In FIG. 1, DI represents an input image signal, HI represents an input horizontal synchronizing signal, and VI represents an input vertical synchronizing signal. Further, HS represents a horizontal synchronizing signal processed by the synchronizing signal processing circuit 5, VS represents a vertical synchronizing signal processed by the synchronizing signal processing circuit 5, DP represents an image signal processed by the image decimation circuit 7, DZ represents an image signal processed by the image scale-up circuit 9, SP represents a drive signal for the display panel 10, and TD represents a control signal. Furthermore, RD represents data such as input signal measurement results generated by the input signal measurement circuit 4.

#FIG. 2 is a block diagram showing configuration of the synchronizing signal processing circuit 5 shown in FIG. 1. As shown in FIG. 2, the synchronizing signal processing circuit 5 has a synchronizing signal decimation circuit 11 and a delay circuit 12. In FIG. 2, VM represents a vertical synchronizing signal processed by the synchronizing signal decimation circuit 11.