Ultra low jitter clock generation device and method for storage drive and radio frequency systems
AssigneeInfineon Technologies AG
InventorSasan Cyrusian
Life of this patent
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Abstract
A clock generation device includes a delay-locked loop and a plurality of programmable counters. The plurality of programmable counters are coupled to delay-locked loop. Each of the programmable counters has a separate output. The delay-locked loop is configured to generate a plurality of phase delay line outputs. A hard drive includes the delay-locked loop and the programmable counters, which generate multiple timing signals such as read, write, servo, and system timing signals. The method of generating timing signals includes delaying an input signal by a programmable delay and generating a plurality of timing pulses through the programmable counters.
Claims23
A clock generation device, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- and
- a plurality of programmable counters directly coupled to the plurality of phase delay lines of the delay-locked loop, the plurality of programmable counters comprising multi-phase counters having common inputs and separate outputs configured to generate separate timing pulses, wherein the delay-locked loop is configured to generate multiple phase outputs.
A clock generation device, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- and
- a plurality of programmable counters directly coupled to the plurality of phase delay lines of the delay-locked loop, the plurality of programmable counters comprising multi-phase accumulators having common inputs and separate outputs configured to generate separate timing pulses, wherein the delay-locked loop is configured to generate multiple phase outputs.
A clock generation device, comprising:
- a delay-locked loop comprising a plurality phase delay lines;
- a phase-locked loop coupled to the delay-locked loop, the delay-locked loop comprising a tunable LC oscillator coupled to an output of the phase-locked loop;
- and
- a plurality of programmable multi-phase counters coupled to the plurality of phase delay lines of the delay-locked loop, wherein each of the plurality of counters comprise common inputs and separate outputs configured to generate separate read, write, servo, and system timing pulses, wherein the delay-locked loop is configured to generate a plurality of phase outputs.
A repetitive storage device, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- and
- a plurality of programmable counters coupled to the delay-locked loop, wherein the plurality of counters comprise multi-phase counters having common inputs coupled to the plurality of phase delay lines and separate outputs, the separate outputs being configured to generate at least one read, write, servo, controller, and interface timing pulses, wherein the delay-locked loop is configured to generate multiple phase outputs.
A repetitive storage device, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- and
- a plurality of programmable counters coupled to the delay-locked loop, wherein the plurality of counters comprise phase accumulators having common inputs coupled to the plurality of phase delay lines and separate outputs, the separate outputs being configured to generate at least one read, write, servo, controller, and interface timing pulses, wherein the delay-locked loop is configured to generate multiple phase outputs.
A hard drive, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- a phase-locked loop coupled to the delay-locked loop, the delay-locked loop comprising a tunable LC oscillator coupled to an output of the phase-locked loop;
- and
- a plurality of programmable multi-phase counters coupled to the delay-locked loop, wherein each of the plurality of counters comprise common inputs coupled to the plurality of phase delay lines and separate outputs, the separate outputs being configured to generate separate read, write, servo, and system timing pulses, wherein the delay-locked loop is configured to generate a plurality phase outputs.
A method of generating timing pulses in a hard drive, comprising:
- delaying an input signal by a programmable delay;
- generating a plurality of phase signals using a delay-locked loop;
- and
- distributing a plurality of timing signals generated by a plurality of multi-phase counters coupled to the delay-locked loop.
A hard drive, comprising:
- a delay-locked loop comprising a plurality of phase delay lines;
- and
- a plurality of programmable counters coupled to the plurality of phase delay lines of the delay-lock loop, wherein the plurality of counters comprise common inputs coupled to the plurality of phase delay lines and separate outputs, the separate outputs generating at least one read, write, servo, system, controller, and interface timing pulses, the read, write, servo, and system clock signals having differing frequencies and wherein the delay-locked loop is configured to generate multiple phase outputs.
Dependencies are inferred from the claim text.