Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor

An integrated circuit comprising:

• a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said signal generation circuit for generating a periodic output signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal;
• and
• a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the periodic output signal accordingly.

An integrated circuit comprising:

• a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said signal generation circuit for generating a periodic output signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal;
• and
• circuit means for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the periodic output signal accordingly.

An integrated circuit comprising:

• a phase locked loop circuit having an input for receiving an externally provided reference clock signal having a frequency substantially equal to any of at least two possible reference frequencies, and for generating a VCO output signal having a nominal frequency related to that of the reference clock signal;
• and
• a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the at least two possible reference clock frequencies is present, and for communicating an indication thereof to the phase locked loop circuit.

In an integrated circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies, a method of determining which reference frequency is provided comprising of:

• generating on the integrated circuit a first signal having a nominal frequency within a predetermined range;
• comparing each of a plurality of signals having a respective frequency related to the externally provided frequency reference signal to the first signal, to determine which of the plurality of signals most closely matches the frequency of the first signal;
• inferring the frequency of the frequency reference signal in accordance with relationship between the signal that most closely matches the frequency of the first signal and the externally provided frequency reference signal, and the nominal frequency of the first signal.

In a system including an integrated circuit responsive to an externally provided frequency reference signal, said integrated circuit having at least two possible modes of operation, a method of communicating a selected mode of operation to the integrated circuit, said method comprising the steps of:

• providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a first reference frequency to select a first mode of operation;
• and
• providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a second reference frequency to select a second mode of operation.

An integrated circuit for recovering separate clock and data signals from an incoming bit-serial clock-encoded data input stream comprising:

• a phase locked loop circuit responsive to the incoming bit-serial clock-encoded data input stream and further responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said phase locked loop circuit including a voltage controlled oscillator (VCO) circuit for generating a VCO output clock signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal;
• and
• a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the VCO output clock signal accordingly.