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US 6,686,797 B1Granted
Temperature stable CMOS device
AssigneeApplied Micro Circuits Corporation
InventorMehmet M. Eker
Life of this patent
Estimating the term…
Abstract
A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.
Claims2
A bias circuit comprising:
- an operational amplifier having a negative input, a positive input, and an output;
- a load resistor having resistor temperature coefficient;
- a first N-channel field effect transistor having a source, and having a drain and a gate connected together and to the positive input, the first N-channel field effect transistor configured to provide, in accordance with a transistor temperature coefficient, a reference voltage to the positive input;
- a second N-channel field effect transistor having a source connected to the negative input and the load resistor, a drain, and a gate connected to the output, the second N-channel field effect transistor configured to provide a bias voltage based on an output voltage produced at the output of the operational amplifier and in accordance with a relationship between the transistor temperature coefficient and the resistor temperature coefficient such that the bias voltage is independent of temperature for temperatures within a temperature range;
- a current mirror responsive to a voltage for providing a current to the drain of the first N-channel field effect transistor and to the drain of the second N-channel field effect transistor;
- the operational amplifier for comparing the reference voltage to a load voltage produced across the load resistor and adjusting the reference current to minimize a difference between the reference voltage and a load voltage produced across the load resistor;
- a P-channel field effect transistor having a source for receiving the voltage, and having a drain and gate connected together;
- a third N-channel field effect transistor having a drain connected to the drain and gate of the P-channel field effect transistor, having a gate connected to the drain and gate of the first N-channel field effect transistor, and having a source;
- a fourth N-channel field effect transistor having a drain for receiving the voltage, having a gate connected to the drain and gate of the P-channel field effect transistor, and having a source connected to the positive input and to the drain and gate of the first N-channel field effect transistor;
- and
- the sources of the first and third N-channel field effect transistors being connected together and to the load resistor.
8 more elements
Dependencies are inferred from the claim text.