Compact self-biasing reference current generator

#This invention relates generally to monolithic reference current generators and, more specifically, to a very compact self-biasing current generator that can be implemented in a bipolar semiconductor process or in a complementary metal oxide semiconductor (CMOS) process.

#In the field of analog integrated circuit (IC) design, it is very common to provide a reference current that is proportional to a reference voltage, the reference current being provided though a current mirror.

#FIG. 1 shows a typical prior art circuit for providing a reference current lout at the output of a current mirror. An operational amplifier forces the junction between resistor R1 and the source terminal of device M1 to a reference voltage Vref, thereby generating a current I that is equal to Vref/R1 through components M1, M2, and R1. While this circuit appears simple, it requires the operational amplifier along with its bias circuit. A reference current generator such as this is often used to provide stable current sources to critical analog circuits inside a chip. If the current generator requires another bias circuit elsewhere in the chip for its own biasing, it increases the size, power requirements, and complexity of the entire current reference circuit. The biasing circuit for the operational amplifier of FIG. 1 will most likely be very simple and inaccurate, causing undesirable errors in the offset, offset drift, and other parameters of the operational amplifier.

#FIG. 1 is a circuit diagram illustrating a typical prior art reference current generator.

#FIG. 2 is a circuit diagram of a reference current generator in accordance with a first embodiment of the present invention.

#FIG. 3 is a circuit diagram of a reference current generator in accordance with a second embodiment of the present invention.

#Referring generally to FIGS. 2 and 3, there are shown detailed circuit diagrams of alternative embodiments of a reference current generator in accordance with the present invention. Both of these circuits operate by the principles illustrated in the circuit diagrams of FIGS. 4A and 4B, which are described in detail hereinbelow. Referring now to FIG. 4A and its equivalent circuit of FIG. B, it is assumed that device pairs MN10 and MN20 and MP10 and MP20 are matched pairs with the same W/L ratio. It is also assumed t at the input voltage reference has a negligible source impedance. The circuits are configured such that the current through devices MN10 and MP10 is equal to the current through devices MN20 and MP20. The operational amplifier 100 of FIGS. 4A and 4B drives the common gate of MN10 and MN20 such that the voltage drops across diode connected PMOSFETs MP10 and MP20, are equal, and thereby forces this condition. The combination of voltage Vref, resistor R1, and resistor R2 is replaced with a voltage source having a value equal to Vref{R2/(R1R2)}and having an output impedance expressed by R1/R2(=R1R2/). Devices MN10 and MN20 operate under the same bias condition, making their gate to source voltages (Vgs) identical. Since MN10 and MN20 share the common gate connection, voltage at their source nodes are the same. Hence, R3 · I = V ⁢ ⁢ r ⁢ ⁢ ef · R2 R1 + R2 + R1 · R2 R1 + R2 · I ( 1 )

#Solving equation (1) for I yields I = R2 R1 + R2 R3 - R1 · R2 R1 + R2 · V ⁢ ⁢ r ⁢ ⁢ ef ( 2 ) = Vref R3 · ( 1 + R1 R2 ) - R1 ⁢ ( 3 )

#As shown by equation (3), this circuit creates a reference current I which is proportional to the reference voltage Vref. The transimpedance is give by the following expression: R3 · ( 1 + R1 R2 ) - R1