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US 6,686,789 B2Granted
Dynamic low power reference circuit
AssigneeAgere Systems Inc.
InventorsDouglas D. Lopata, Bernard Lee Morris
Life of this patent
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AssigneeAgere Systems Inc.
InventorsDouglas D. Lopata, Bernard Lee Morris
Estimating the term…
A dynamic low power reference circuit includes a reference source for generating a reference voltage and/or a reference current. The reference circuit further includes an activity detector configured to measure an activity level of at least a portion of another circuit coupled to the reference circuit and to generate a control signal representative of the activity level. A controller coupled to the reference source is configured to dynamically change an output impedance of the reference circuit in response to the control signal. The techniques of the present invention thus provide a reference circuit that is capable of dynamically changing an output impedance associated therewith, such that when activity on one or more nodes in the other circuit is detected within a time period, the output impedance of the reference circuit is at a first value which is sufficiently low so as to reduce the likelihood of noise being coupled onto the output of the reference circuit. Alternatively, when essentially no activity on the one or more nodes is detected within the time period, the output impedance of the reference circuit is at a second value which is greater than the first value, thereby reducing power consumption in the reference circuit.
A reference circuit comprising:
A reference circuit comprising:
A reference circuit comprising:
An integrated circuit including one or more reference circuits, at least one of the reference circuits comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Term ended 28 Mar 2022 (estimated)
The present invention relates generally to reference circuits, and more particularly relates to a dynamic low power reference circuit.
Many circuits employed in a variety of system applications require a reference source (e.g., reference voltage or reference current), in addition to traditional power supply voltages (e.g., VDD and VSS). With respect to a particular circuit or system, the reference source may be generated either internally or externally. In either case, the reference source consumes a certain amount of quiescent or direct current (DC) power.
It is advantageous, especially in portable devices and other low power systems, to minimize the amount of power consumed by the reference source. Quite often, in order to conserve power, a single reference source is utilized in conjunction with a global reference conductor (e.g., bias line) for supplying a reference voltage or reference current to multiple circuits which may be distributed across an integrated circuit (IC) device. For example, the global reference conductor is typically routed throughout the IC to all sub-circuits which utilize the reference voltage or current. In this manner, the need for individual local reference sources within each sub-circuit may be eliminated, thus reducing overall DC power consumption in the IC. However, the routing of the reference conductor throughout the IC can be difficult, particularly in densely fabricated ICs where interconnect space is already scarce. Furthermore, capacitive coupling associated with such a reference conductor may induce noise onto the conductor, thus corrupting the reference voltage or current. The noise may be generated, for example, by the switching of digital circuits, crosstalk, etc. as may be present in the IC.
FIG. 1 is a block diagram depicting an integrated circuit including analog/digital circuitry and a reference circuit, formed in accordance with the present invention.
FIG. 2 is a schematic diagram illustrating an exemplary reference circuit, formed in accordance with one aspect of the present invention.
FIG. 3 is a schematic diagram illustrating a more detailed view of an exemplary activity detector of the FIG. 2 reference circuit, formed in accordance with one aspect of the present invention.
The present invention will be described herein in the context of an illustrative reference circuit. The reference circuit may be used, for example, in conjunction with other analog and/or digital circuitry in an integrated circuit (IC) device. It should be appreciated, however, that the present invention is not limited to this or any particular reference circuit and/or application. Rather, the invention is more generally applicable to providing a reference circuit that is configured to have an output impedance which dynamically changes in response to a detected activity level of one or more circuits using or otherwise associated with the reference circuit. Moreover, although implementations of the present invention are described herein with specific reference to metal-oxide-semiconductor (MOS) transistor devices, it is to be appreciated that the invention is not limited to such transistors, and that other suitable transistors, such as, for example, bipolar junction transistors (BJTs), may be similarly employed, as will be understood by those skilled in the art.
FIG. 1 illustrates a block diagram of an IC device 100 which may include a reference circuit 102 and other analog/digital circuitry 104. It is to be appreciated that the analog/digital circuitry 104 may comprise analog circuits, digital circuits, or a combination of both analog and digital circuits. Reference circuit 102 preferably generates a substantially constant reference output, which may be, for example, a reference voltage VREF. The present invention, however, contemplates that the reference output may be a reference current as well. The analog/digital circuitry 104 preferably utilizes the reference output VREF generated by the reference circuit 102, which is presented to an input REF IN of the analog/digital circuitry 104.
The reference circuit 102 includes an input for receiving an activity level signal A. The activity level signal, which may be an analog or a digital signal, is preferably indicative of a measured activity level of a particular node or nodes in the analog/digital circuitry 104. In the case of a digital signal, for example, the activity level signal maybe a logic high (e.g., VDD) when either a high-to-low or a low-to-high transition is detected at the particular node. Various techniques for measuring the activity level are contemplated by the present invention, including, but not limited to, detecting a change in the voltage level or current level at a given node(s) within a predetermined time interval.