US 6,686,788 B2 · Delay circuit of clock synchronization device using delay cells having wide delay range

Abstract

A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.

Claims18

Dependent claims

A delay circuit for a clock synchronization device having a plurality of unit delay cells connected in series, wherein each unit delay cell comprises:

a variable current source having a current value adjusted according to a current control voltage;
a variable resistance unit having a resistance value adjusted according to a resistance control voltage, wherein the variable resistance unit includes a cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell;
an input device connected between the output terminals and the variable current source and configured to receive output signals from a previous unit delay cell;
and
wherein the variable resistance unit further comprises:
a plurality of first PMOS transistors having gates connected to the resistance control voltage and commonly connected sources that are connected to a supply voltage;
a plurality of second PMOS transistors having gates respectively connected to the output terminals and commonly connected sources that are connected to the supply voltage;
and
third and fourth PMOS transistors having commonly connected sources that are connected to the supply voltage and having gates that are respectively cross-coupled to the output terminals.

6 more elements

A delay circuit for a clock synchronization device comprising:

an operational amplifier configured to set a level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage;
a delay unit that includes a plurality of unit delay cells connected in series, each of the plurality of unit delay cells having a delay time that is set according to a resistance control voltage and the current control voltage;
and
a replica bias unit configured to output the regulation voltage according to the resistance control voltage and the current control voltage;
wherein each of the plurality of unit delay cells further includes:
a first variable current source having a first current value adjusted according to the current control voltage;
a first variable resistance unit having a first resistance value adjusted according to the resistance control voltage, wherein the first variable resistance unit includes a first cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell;
and
a first input device connected between the output terminals and the first variable current source and configured to receive output signals of a previous unit delay cell;
and
wherein the replica bias unit further comprises:
a second variable current source having a second current value adjusted according to the current control voltage;
a second variable resistance unit that includes a second cross-coupled adjustment device and having a second resistance value adjusted according to the resistance control voltage;
and
a second input device connected between the second variable current source and the second variable resistance unit and further connected to a supply voltage and the reference voltage
wherein the second variable resistance unit and the second input device have a common node configured to form output terminals.

13 more elements

A delay circuit for a clock synchronization device comprising:

an operational amplifier configured to set a level of a current control voltage according to a voltage difference between a regulation voltage and reference voltage;
a delay unit that includes a plurality of unit delay cells connected in series, each of the plurality of unit delay cells having a delay time that is set according to a resistance control voltage and the current control voltage;
and
a replica bias unit configured to output the regulation voltage according to the resistance control voltage and the current control voltage;
wherein each of the plurality of unit delay cells further includes:
first variable current source having a first current value adjusted according to the current control voltage;
a first variable resistance unit having a first resistance value adjusted according to the resistance control voltage, wherein the first variable resistance unit includes a first cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell;
and
a first input device connected between the output terminals and the first variable current source and configured to receive output signals of a previous unit delay cell wherein the first variable resistance unit further comprise:
a plurality of first PMOS transistors having gates connected to the resistance control voltage and commonly connected sources that are connected to a supply voltage;
a plurality of second PMOS transistors having gates respectively connected to the output terminals and commonly connected sources that are connected to the supply voltage;
and
third and fourth PMOS transistors having commonly connected sources that are connected to the supply voltage and having gates that are respectively cross-coupled to the output terminals.

10 more elements

A delay circuit for a clock synchronization device comprising:

an operational amplifier configured to set a level of a current control voltage according to a voltage difference between a regulation voltage and reference voltage;
a delay unit that includes a plurality of unit delay cells connected in series, each of the plurality of unit delay cells having a delay time that is set according to a resistance control voltage and the current control voltage;
and a replica bias unit configured to output the regulation voltage according to the resistance control voltage and the current control voltage;
wherein each of the plurality of unit delay cells further includes:
a first variable current source having a first current value adjusted according to the current control voltage:
a first variable resistance unit having a first resistance value adjusted according to the resistance control voltage, wherein the first variable resistance unit includes a first cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell;
and
a first input device connected between the output terminals and the first variable current source and configured to receive output signals of a previous unit delay cell wherein the first variable resistance unit further comprises:
a plurality of first NMOS transistors having gates connected to the resistance control voltage and commonly sources that are connected to a ground voltage;
a plurality of second NMOS transistors having gates respectively connected to the output terminals and commonly connected sources that are connected to the ground voltage;
and
third and fourth NMOS transistors having common source connected to the ground voltage and gates respectively cross-coupled to said output terminals.

9 more elements

A delay circuit for a clock synchronization device comprising:

an operational amplifier configured to set a level of a current control voltage according to a voltage difference between a regulation voltage and reference voltage;
a delay unit that includes a plurality of unit delay cells connected in series, each of the plurality of unit delay cells having a delay time that is set according to a resistance control voltage and the current control voltage;
and
a replica bias unit configured to output the regulation voltage according to the resistance control voltage and the current control voltage;
wherein each of the plurality of unit delay cells further includes:
a first variable current source having a first current value adjusted according to the current control voltage;
a first variable resistance unit having a first resistance value adjusted according to the resistance control voltage, wherein the first variable resistance unit includes a first cross-coupled adjustment device and outputs output signals through output terminals to a next unit delay cell;
a first input device connected between the output terminals and the first variable current source and configured to receive output signals of a previous unit delay cell;
and
wherein the replica bias unit further comprises
a second variable current source having a second current value adjusted according to the current control voltage;
a second variable resistance unit that includes a second cross-coupled adjustment device and having a second resistance value adjusted according to the resistance control voltage;
and
a second input device connected between the second variable current source and the second variable resistance unit and further connected to a supply voltage and the reference voltage;
wherein the second variable resistance unit and the second input device have a common node configured to form output terminals;
wherein the first variable resistance unit further comprises a plurality of first PMOS transistors having gates connected to the resistance control voltage and commonly connected sources that are connected to a supply voltage;
a plurality of second PMOS transistors having gates respectively connected to the output terminals and commonly connected sources that are connected to the supply voltage;
and
third and fourth PMOS transistors having commonly connected sources that are connected to the supply voltage and having gates that are respectively cross-coupled to the output terminals.

16 more elements

Dependencies are inferred from the claim text.

Delay circuit of clock synchronization device using delay cells having wide delay range

Life of this patent

Delay circuit of clock synchronization device using delay cells having wide delay range

Life of this patent

Abstract

Claims18