Deskewing global clock skew using localized DLLs

#A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system. FIG. 1 shows a typical computer system (10) having a microprocessor (12), memory (14), integrated circuits (16) that have various functionalities, and communication paths (18), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (10).

#The components of a computer system use a reference of time to perform the various operations of the computer system. This reference of time is provided to the components of the computer system using one or more clock signals. The components use the one or more clock signals to determine when to conduct certain operations. As computer systems continue to operate at ever-increasing frequencies, it becomes more and more important to ensure that the components of a computer system receive their clock signals in an accurate and timely manner because a mistiming has the potential to cause an error, performance setback, or an outright malfunction of the computer system.

#FIG. 2 shows a clock distribution network (20) for a microprocessor (12). A reference clock (also known in the art as “system clock” and shown in FIG. 2 as REF_CLK), which is typically generated from outside the microprocessor (12), serves as an input to a phase locked loop (“PLL”) (15). Essentially, the PLL (15) uses feedback to maintain a specific phase relationship between its output (shown in FIG. 2 as CHIP_CLK) and the reference signal. The chip clock from the PLL (15) is then distributed to one or more clock drivers/buffers (17), which, in turn, distribute the chip clock to a global clock grid (19), where the global clock grid (19) feeds the chip clock to various microprocessor components such as local clock grids (24) and a feedback loop (26) that feeds the chip clock back to the PLL (14). The local clock grids (24) feed the chip clock to base components of the microprocessor (12), such as latches (22) and flip-flops (28).

#FIG. 1 shows a typical computer system.

#FIG. 2 shows a typical clock distribution network.

#FIG. 3 shows a typical clock distribution network.

#Embodiments of the present invention relate to a method for reducing global clock skew in an integrated circuit. Embodiments of the present invention further relate to a circuit device implementation that reduces global clock skew. Embodiments of the present invention further relate to a technique for increasing computer system performance by reducing system uncertainties associated with clock skew in the computer system.

#Particularly, the present invention relates a technique for referencing a point on a clock grid for which to align other points on the clock grid by varying one or more delays of clock buffers associated with the clock grid. This technique helps decrease clock skew by reducing systematic components of clock skew in an integrated circuit.

#FIG. 4a shows an exemplary component layout of an integrated circuit (80) in accordance with an embodiment of the present invention. In FIG. 4a, a plurality of sections (87) of the integrated circuit (80) each have a phase detector (86) (shown in FIG. 4a as PD) and a clock delay circuit (84) (shown in FIG. 4a as CDC). A phase detector (86) and a clock delay circuit (84) in the same section (87) are said to be “associated.” Each phase detector (86) inputs a reference clock signal and a feedback signal from a portion of a clock grid (94) controlled by the clock delay circuit (84) associated with the phase detector (86). Dependent on a phase difference between the reference clock signal and the feedback signal, the phase detector (86) outputs a signal to its associated clock delay circuit (84) indicating whether to speed up or slow down the portion of the clock arid (94) connected to the associated clock delay circuit (84). The reference clock signal input to a particular phase detector (86) may be connected to an output of the DLL (82) or to another portion of clock grid (94) that is controlled by a clock delay circuit (84) not associated with the particular phase detector (86).