Hybrid phase-locked loop

#1. Field of the Invention

#The present invention generally relates to a phase-locked loop (PLL) and, more particularly, to a hybrid phase-locked loop with digital processing and analog processing mixed therein.

#2. Description of the Prior Art

#The objects, spirits and advantages of the preferred embodiment of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein:

#FIG. 1 is a schematic block diagram showing a conventional analog phase-locked loop;

#FIG. 2 is a schematic block diagram showing a hybrid phase-locked loop in accordance with the present invention;

#The present invention providing a hybrid phase-locked loop can be exemplified by the preferred embodiment and the accompanied drawings as described hereinafter. In the prior-art PLL design, there is a dilemma situation when it comes to suppression of the jitter of the reference signal as well as the jitter of the oscillation signal from the voltage-controlled oscillator. However, in the present invention, the hybrid phase-locked loop suppresses the jitter of the reference signal by using digital processing and suppresses the jitter of the voltage-controlled oscillator by using analog processing.

#FIG. 2 is a schematic diagram showing a hybrid phase-locked loop in accordance with the present invention. As shown in FIG. 2, the hybrid phase-locked loop 20 comprises: a phase-frequency detector 21; a digit pump 22; a digital filter 23; a digit-controlled oscillator 24; a phase selector 25; a multi-phase frequency generator 26; an analog phase-locked loop 27; and a frequency divider 28. More particularly, the phase-frequency detector 21, the digit pump 22, the digital filter 23, the digit-controlled oscillator 24, the phase selector 25 and the frequency divider 28 are included in digital processing, while the multi-phase frequency generator 26 and the analog phase-locked loop 27 are included in analog processing.

#The phase-frequency detector 21 detects the phase difference between the reference signal Fref and the oscillation feedback signal Fb and outputs a phase-difference signal PE. The phase-difference signal PE is a digit signal, indicating the number of pulses generated by the mean-frequency signal Fav during the phase-difference period between the reference signal Fref and the oscillation feedback signal Fb. The reference signal Fref is the horizontal synchronous signal (HSYNC) in a LCD controller chip. FIG. 3 is a timing diagram showing waveforms of a reference signal, an oscillation feedback signal and a phase-difference signal. As shown in FIG. 3, the larger the phase difference between the reference signal Fref and the oscillation feedback signal Fb is, the longer the phase-difference period would be, resulting in a larger phase-difference signal PE.