Power-on reset system
AssigneeAnalog Devices, Inc.
InventorYuhong Huang
Life of this patent
Estimating the term…
Abstract
A power-on reset system insensitive to the ramp up rate of supply voltage VDD includes two power-on reset circuits. The first reset circuit asserts a reset signal RS1 when supply voltage VDD ramps up to its rated voltage. The second reset circuit produces a first reference voltage VR1 and a second reference voltage VR2 which is delayed with respect to VR1, and asserts a reset signal RS2 when VR1 is greater than VR2. A logic gate asserts a reset signal RS3 when either RS1 or RS2 is asserted; RS3 is the output of the power-on reset system, and is asserted whether one or both of reset signals RS1 and RS2 is asserted. Both reset circuits are preferably arranged to operate with supply voltages of 2 volts or less.
Claims13
A power-on reset system, comprising:
- a supply voltage VDD which ramps from 0 volts to a rated voltage,
- a first power-on reset circuit arranged to assert a first reset signal RS1 as VDD ramps from 0 volts to said rated voltage,
- a second power-on reset circuit comprising:
- a first reference voltage generator which produces a first reference voltage VR1 as VDD ramps from 0 volts to said rated voltage,
- a second reference voltage generator which produces a second reference voltage VR2 as VDD ramps from 0 volts to said rated voltage which is delayed with respect to the generation of said first reference voltage VR1, said first and second reference voltage generators arranged such that VR2>VR1 when VDD is at its rated voltage, and
- a first comparator which receives VR1 and VR2 at respective inputs and which asserts a second reset signal RS2 when VR1>VR2, and
- a logic gate which receives RS1 and RS2 at respective inputs and which asserts a reset signal RS3 when either RS1 or RS2 is asserted, said RS3 being the output of said power-on reset system.
A power-on reset system, comprising:
- a supply voltage VDD which ramps from 0 volts to a rated voltage,
- a first power-on reset circuit comprising:
- a first reference voltage generator which produces a first reference voltage VR1 as VDD ramps from 0 volts to said rated voltage, and
- a voltage generator which produces a voltage V2 that tracks VDD,
- said first power-on reset circuit arranged to assert a first reset signal RS1 when VR1>V2,
- a second power-on reset circuit comprising:
- a second reference voltage generator which produces a second reference voltage VR2 when VDD ramps from 0 volts to said rated voltage which is delayed with respect to the generation of said first reference voltage VR1, and
- a first comparator which receives VR1 and VR2 at respective inputs and which asserts a second reset signal RS2 when VR1>VR2, said first and second reference voltage generators arranged such that VR2>VR1 when VDD is at its rated voltage, and
- a logic gate which receives RS1 and RS2 at respective inputs and which asserts a reset signal RS3 when either RS1 or RS2 is asserted, said RS3 being the output of said power-on reset system.
A power-on reset system, comprising:
- a supply voltage VDD which ramps from 0 volts to a rated voltage,
- a first power-on reset circuit comprising:
- a first reference voltage generator which produces a first reference voltage VR1 as VDD ramps from 0 volts to said rated voltage, and
- a voltage generator which produces a voltage V2 that tracks VDD, and
- a first comparator which receives VR1 and V2 at respective inputs and which asserts a first reset signal RS1 when VR1>V2,
- a second power-on reset circuit comprising:
- a second reference voltage generator which produces a second reference voltage VR2 when VDD ramps from 0 volts to said rated voltage,
- a time delay circuit which delays the generation of VR2 with respect to the generation of VR1, and
- a second comparator which receives VR1 and VR2 at respective inputs and which asserts a second reset signal RS2 when VR1>VR2, said first and second reference voltage generators arranged such that VR2>VR1 when VDD is at its rated voltage,
- wherein said first voltage reference generator is arranged such that VR1 tracks V2 over temperature so that the VDD voltage at which VR1=V2 is approximately temperature independent, and
- a logic gate which receives RS1 and RS2 at respective inputs and which asserts a reset signal RS3 when either RS1 or RS2 is asserted, said RS3 being the output of said power-on reset system.
Dependencies are inferred from the claim text.