Frequency divider with selectable division factor

A frequency divider comprising:

• a plurality of serially-connected data storage units which temporarily hold data input based, on control by an input control signal, wherein data output from each storage unit is input into an immediately subsequent storage unit;
• a clock inversion circuit which is supplied with an output of a final data storage unit of said plurality of data storage units and a clock signal of original oscillation, which inverts logic of the clock signal at a change of the output of said final data storage unit to produce a logic inverted clock signal, and which supplies the logic inverted clock signal to odd-numbered data storage units and even-numbered data storage units of said plurality of data storage units in a complementary manner as the input control signal;
• an inversion-delay circuit comprising an inverter which inverts logic of the output of said final data storage unit, and a delay processing circuit which delays the output of said final data storage unit for a predetermined time, wherein said inversion-delay circuit inputs the output delayed to a data input of a first data storage unit of said plurality of data storage units;
• and
• a gate circuit which switches whether the output of said final data storage unit is input to said clock inversion circuit, wherein either frequency division with a division factor of an even number or frequency division with a division factor of an odd number is selected by said gate circuit.

A frequency divider comprising:

• a plurality of serially-connected data storage units which temporarily hold data input based, on control by an input control signal, wherein data output from each storage unit is input into an immediately subsequent storage unit;
• a clock inversion circuit which is supplied with an output of a final data storage unit of said plurality of data storage units and a clock signal of original oscillation, which inverts logic of the clock signal at a change of the output of said final data storage unit to produce a logic inverted clock signal, and which supplies the logic inverted clock signal to odd-numbered data storage units and even-numbered data storage units of said plurality of data storage units in a complementary manner as the input control signal;
• an inversion-delay circuit comprising an inverter which inverts logic of the output of said final data storage unit, and a delay processing circuit which delays the output of said final data storage unit for a predetermined time, wherein said inversion-delay circuit inputs the output delayed to a data input of a first data storage unit of said plurality of data storage units;
• and
• a digital delay circuit which provides the output of said final data storage unit with a preset delay corresponding to n periods of the clock signal, and receives the output delayed to said clock inversion circuit, wherein a frequency division factor can be altered by changing n, and n is an integer.

A frequency divider comprising:

• a plurality of serially-connected data storage units which temporarily hold data input based, on control by an input control signal, wherein data output from each storage unit is input into an immediately subsequent storage unit;
• a clock inversion circuit which is supplied with an output of a final data storage unit of said plurality of data storage units and a clock signal of original oscillation, which inverts logic of the clock signal at a change of the output of said final data storage unit to produce a logic inverted clock signal, and which supplies the logic inverted clock signal to odd-numbered data storage units and even-numbered data storage units of said plurality of data storage units in a complementary manner as the input control signal;
• an inversion-delay circuit comprising an inverter which inverts logic of the output of said final data storage unit, and a delay processing circuit which delays the output of said final data storage unit for a predetermined time, wherein said inversion-delay circuit inputs the output delayed to a data input of a first data storage unit of said plurality of data storage units, wherein
• said plurality of data storage units are trigger level data storage units,
• said frequency divider further comprises switchover circuits which switch whether some data storage units included in said plurality of data storage units are always brought into a data-through state, and
• frequency division factor can be altered by switching of said switch-over circuits.

A frequency divider comprising:

• a plurality of serially-connected data storage units which temporarily hold data input based, on control by an input control signal, wherein data output from each storage unit is input into an immediately subsequent storage unit;
• a clock inversion circuit which is supplied with an output of a final data storage unit of said plurality of data storage units and a clock signal of original oscillation, which inverts logic of the clock signal at a change of the output of said final data storage unit to produce a logic inverted clock signal, and which supplies the logic inverted clock signal to odd-numbered data storage units and even-numbered data storage units of said plurality of data storage units in a complementary manner as the input control signal;
• an inversion-delay circuit comprising an inverter which inverts logic of the output of said final data storage unit, and a delay processing circuit which delays the output of said final data storage unit for a predetermined time, wherein said inversion-delay circuit inputs the output delayed to a data input of a first data storage unit of said plurality of data storage units, wherein
• said plurality of data storage units are edge trigger data storage units,
• said frequency divider further comprises switchover circuits among said plurality of data storage units, each of said switchover circuits switching between an output of an immediately preceding data storage unit and an output of a third data storage unit upstream from said switchover circuit, and
• frequency division factor can be altered by switching of said switch-over circuits.