Phase detector having improved timing margins

A phase detector comprising:

• an input for receiving data signals;
• an input for receiving clock signals;
• circuitry for retiming data received at said data input;
• a plurality of multi-input gates, said gate inputs arranged in conjunction with different combinations of data signals retimed by said retiming circuitry, with unretimed data signals, with clock signals received from said clock input;
• and with the inverse of said clock signals, such that the linearly combined output of said gates is a signal at said output for providing pulses proportional to the phase difference between said data pulses received at said data input and clock pulses received said clock input.

A phase detector comprising:

• an input for receiving data signals;
• an input for receiving clock signals;
• an output for providing phase control signals;
• data retiming circuiting for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom;
• a plurality of gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit;
• and
• a combiner for mixing the outputs of at least two of said gates.

Circuitry for determining phase between a data signal and a clock signal, said circuitry comprising:

• a first circuit for retiming provided even data signals;
• a second circuit for retiming provided odd data signals;
• a plurality of three-input AND gates;
• a first input of a first gate and a first input of a third gate is said unretimed data signal that has been inverted;
• a second input of said first gate is said even retimed data signal;
• a second input of a second gate is said even retimed data signal inverted;
• a third input of said first gate is said clock signal;
• a first input of said second gate and a first input of a fourth gate is said unretimed data signal;
• a second input of said third gate is said odd retimed data signal;
• a second input of said fourth gate is said odd retimed data signal inverted
• a third input of said third gate and a third input of said fourth gate is said clock signal inverted;
• and
• a combiner for summing the outputs from said AND gates.

Circuitry for determining phase between a data signal and a clock signal, said circuitry including:

• a first circuit for retiming provided even data signals;
• a second circuit for retiming provided odd data signals;
• a plurality of three-input AND gates;
• a plurality of two-input exclusive OR gates and a plurality of two-input AND gates;
• a first input of a first exclusive OR gate is said even retimed data signals;
• a second input of said first exclusive OR gate and a first input of a second exclusive OR gate is said unretimed data signals;
• a second input of said second exclusive OR gate is said odd retimed data signals;
• a first input to a first AND gate is the out put of said first exclusive OR gate;
• a second input to said fist AND gate is said clock signal;
• a first input to a second AND gate is the output of said second exclusive OR gate;
• a second input to said second AND gate is said clock signal inverted;
• and
• a combiner for summing the outputs of said AND gates.