Digital data coincidence determining circuit

#The present invention relates to a digital data coincidence determining circuit, and, more particularly, to a coincidence determining circuit which determines whether plural pieces of digital data coincide with one another by comparing the digital data bit by bit.

#There is an address comparator for a memory circuit, which determines whether two pieces of digital data coincide with each other by comparing the two pieces of digital data bit by bit. FIG. 1 is a schematic circuit diagram of a conventional coincidence determining circuit 100. The coincidence determining circuit 100 determines whether two pieces of digital data A and B each consisting of n bits coincide with each other. The digital data A consists of bits A0, A1, . . . , An−1 and the digital data B consists of bits B0, B1, . . . , Bn−1. The complementary values of the individual bits of the digital data A are /A0, /A1, . . . , /An−1 and the complementary values of the individual bits of the digital data B are /B0, /B1, . . . , /Bn−1. The coincidence determining circuit 100 includes exclusive OR circuits XOR0, XOR1, . . . , XORn−1 for determining whether the digital data A and B coincide with each other by comparing the digital data A and B bit by bit. Each of the exclusive OR circuits XOR0, XOR1, . . . , XORn−1 generates a signal of a logical level “L” (Low) when the associated two bits coincide with each other, and generates a signal of a logical level “H” (High) when there is no coincidence.

#The output signals of the exclusive OR circuits XOR0, XOR1, . . . , XORn−1 are applied to the gates of n-channel transistors TNS′0, TNS′1, . . . , TNS′n−1. Each transistor is connected between a wiring 110, which is precharged to a high potential in a given clock cycle, and the ground. In case where at least one of the bits of the digital data A does not coincide with the associated bit of the digital data B, that transistor which is connected to the associated exclusive OR circuit is turned on, thus electrically connecting the wiring 110 to the ground. In case where all of the bits of the digital data A coincide with the associated bits of the digital data B, all of the transistors are turned off, thus electrically disconnecting the wiring 110 from the ground.

#The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:

#FIG. 1 is a schematic circuit diagram of a conventional digital data coincidence determining circuit;

#FIG. 2 is a schematic circuit diagram of a digital data coincidence determining circuit according to a first embodiment of the present invention;

#In the drawings, like numerals are used for like elements throughout.

#FIG. 2 is a circuit diagram of a digital data coincidence determining circuit 200 according to the first embodiment of the present invention. The coincidence determining circuit 200 determines whether digital data A (A0,A1, . . . , An−1) and digital data B (B0,B1, . . . , Bn−1) each consisting of n bits coincide with each other.

#The coincidence determining circuit 200 includes bit comparison circuits C0, . . . , Cn−1 which determine whether the digital data A and B coincide with each other bit by bit (A0with B0, A1 with B1, . . . , An−1 with Bn−1). Each bit comparison circuit pulls down the potential of a wiring 10 to the ground potential when the data bits do not coincide with each other.