Voltage mode differential driver and method

#1. Field of the Invention

#The invention relates to input/output (I/O) interface circuitry for high speed data communications applications. More specifically the invention relates to low voltage differential signaling (LVDS) drivers, for use in the fields of communications, video and other integrated circuits that demand very high data transfer rates.

#2. Description of the Related Art

#The objects and features of the invention will be more readily understood with reference to the following description and the attached drawings, wherein:

#FIG. 1 is an illustration of a prior art LVDS driver;

#FIG. 2 is an illustration of a prior art LVDS driver having terminal resistors;

#FIG. 3 is an illustration of a voltage mode differential driver according to an embodiment of the present invention. The differential driver includes two Voltage Controlled Voltage Sources (VCVS) 210 and 211, which provide DC voltages to the nodes Vhigh and Vlow, respectively. The output impedance for voltage controlled voltage source 210 is modeled by a resistor 202 and is configured to be a low impedance in the range of a few hundred ohms, preferable around 30 ohms for a differential load of 100 ohms. Similarly, the output impedance for the voltage controlled voltage source 211 is modeled by resistor 203 and is similarly configured to be a low impedance. VCVS 210 and 211 are biased by bias voltages Vb1 and Vb2, respectively output by a bias generator 215.

#The differential driver also includes a switching circuit having a plurality of switches for switching an output voltage (signal) based on an input signal. The switching circuit may include a pair of voltage inputs, at nodes Vhigh and Vlow, and series of switches. In this example, the switching circuit includes two pair of switching transistors 110a, 111a and 120a, 121a, which act as the switches. A signal output, Vout1 and Vout2, are output from the switching circuit to nodes 131 and 132 across a resistive load 130. Load 130 may typically be 100 ohms, but can vary depending on the application. Load 130 may be a differential load, and accordingly, may be grounded in the middle of the load. As a differential load, load 130 would include 50 ohms above the ground and 50 ohms below the ground. Output node 131 is connected to the drains of transistors 110a and 120a, and output node 132 is connected to the drains of transistors 121a and 111a.

#In normal operation, only a single pair of switching transistors will be ON while the other is OFF, in order to allow a current to flow from VCVS 210 through the load 130 to VCVS 211. In the present embodiment, switching transistors 110a and 121a are PMOS transistors, and switching transistors 120a and 111a are NMOS transistors. PMOS transistors are used on the top of the switching circuit because the common mode voltage is around half of the supply voltage, or about 1.2V. The PMOS transistors could have a smaller size than that of NMOS transistors. If NMOS were used, the size would be very big comparatively, because of the Vgs required to turn the switching transistor completely ON. If NMOS transistors were used, then there is a risk of common mode voltage drifting, which will place the common mode voltage outside of the LVDS standard for LVDS applications.