Technique to reduce reflections and ringing on CMOS interconnections

#This invention relates to interconnections within a computer, in particular, to a method and apparatus capable of minimizing reflections, ringing, and delay on long CMOS interconnections in an integrated circuit, between integrated circuits, and between integrated circuits and other circuits.

#Recent efforts in interconnections have revolved around minimizing the resistivity of the metals, in particular copper metallurgy for CMOS integrated circuits, used in interconnections. The problem is that minimizing the resistivity on long interconnection lines is not always the optimum solution when signal quality is also an important factor. The use of long interconnection lines where the resistivity is minimized may lead to problems with ringing and reflections on the line.

#A typical long interconnection line, long being defined as an interconnection line of about 1 cm long or longer, would be a clock distribution line which is used to send clock signals to destination points within an integrated circuit or printed circuit board. Clock signal delay or skew, caused by the characteristics of the distribution line, is an important factor in the transmission of clock signals and for this reason many interconnection or distribution lines attempt to minimize resistivity. However, if signal quality at the destination point is important then consideration must also be given to minimize the reflections and ringing along the line.

#FIG. 1 is a schematic diagram of circuit with an interconnection line;

#FIG. 2 is a graph illustration of a signal propagated through an interconnection line circuit which has a characteristic of an under-damped system;

#FIG. 3 is a graph illustration of a signal propagated through an interconnection line circuit which has a characteristic of an over-damped system;

#The present invention will now be described in connection with FIGS. 1-6. Other embodiments may be utilized and structural or logical changes may be made to the disclosed embodiments and equivalents substituted without departing from the spirit of scope of the present invention.

#Referring to FIG. 1, a circuit is shown which incorporates a signal source 5 which has an output impedance Zs, a long interconnection line 6, and a destination point D1. The long interconnection line 6 has an overall impedance Zo shown as line resistance RL, inductance LL, and capacitance CL. The long interconnection line 6 begins at node N2 and terminates at node N3. Connected to node N3 is a termination line with a small capacitance CS.

#A signal generated by signal source 5 is transmitted along the long interconnection line 6, from node N2 to node N3, and ultimately to a destination point D1. There is a reflection at node N3 back towards N2 due to the fact that there is a small capacitance CS coupled to node N3. The reflected signal will be received back at node N2 and, depending on the impedance of the line Zo and the impedance of the source Zs, the reflected signal will either be reflected again, back towards node N3, or there will be no reflection at all.