US 6,686,765 B2Granted

GTL+ driver

AssigneeSilicon Graphics, Inc.

InventorRodney Ruesch

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Abstract

A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.

Drawings

Claims21

Dependent claims

An integrated circuit driver comprising:

an output node for coupling to a load and providing a first voltage level at a predetermined impedance, the first voltage level corresponding to a logic high level, and providing a second voltage level at the predetermined impedance, the second voltage level corresponding to a logic low level, and presenting a high impedance state;
a first switched resistive element coupled to the output node and also coupled to a first voltage source;
a second switched resistive element coupled to the output node and also coupled to a ground potential;
a third switched resistive element coupled to the output node and also coupled to the ground potential;
a first control line coupled to the first switched resistive element, the first control line for actuating the first switched resistive element;
a second control line coupled to the second switched resistive element, the second control line for actuating the second switched resistive element;
a third control line coupled to the third switched resistive element, the third control line for actuating the third switched resistive element;
and
a predriver having a first node coupled to the first control line and a second node coupled to the second control line, the predriver adapted to provide a predetermined edge rate;
and
wherein the load is a resistive load coupled to a third voltage source and wherein the first voltage level, the second voltage level and the predetermined impedance remain substantially constant with variations in manufacturing process, variations in the first voltage source and variations in operating temperature.

8 more elements

A driver comprising:

an output section, including:
an output node;
a plurality of P-nodes;
a first plurality of P-channel transistors, each P-channel transistor of the first plurality of P-channel transistors having a source coupled to a supply voltage and a drain coupled to the output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the first plurality of P-channel transistors;
a plurality of N-nodes;
a first plurality of N-channel transistors, each N-channel transistor of the first plurality of N-channel transistors having a drain coupled to the output node and a source coupled to a ground potential relative to the supply voltage wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the first plurality of N-channel transistors;
and
a second plurality of N-channel transistors, each N-channel transistor of the second plurality of N-channel transistors having a drain coupled to the output node and a source coupled to the ground potential wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the second plurality of N-channel transistors;
and
a first predriver section including:
a P-output node;
a second plurality of P-channel transistors, each P-channel transistor of the second plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the P-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the second plurality of P-channel transistors;
a third plurality of N-channel transistors, each N-channel transistor of the third plurality of N-channel transistors having a drain coupled to the P-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the third plurality of N-channel transistors;
an N-output node;
a third plurality of P-channel transistors, each P-channel transistor of the third plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the N-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the third plurality of P-channel transistors;
and
a fourth plurality of N-channel transistors, each N-channel transistor of the fourth plurality of N-channel transistors having a drain coupled to the N-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fourth plurality of N-channel transistors;
and
wherein the P-output node is coupled to the source of each P-channel transistor of the first plurality of P-channel transistors and further wherein the N-output node is coupled to the source of each N-channel transistor of the first plurality of N-channel transistors;
and
a second predriver section including:
a T-node;
a fourth plurality of P-channel transistors, each P-channel transistor of the fourth plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the T-node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the fourth plurality of P-channel transistors;
and
a fifth plurality of N-channel transistors, each N-channel transistor of the fifth plurality of N-channel transistors having a drain coupled to the T-node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fifth plurality of N-channel transistors;
and
wherein the T-node is coupled to the source of each of the second plurality of N-channel transistors of the output section.

24 more elements

Dependencies are inferred from the claim text.

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Abstract

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Drawings

Claims21

Dependent claims

An integrated circuit driver comprising:

an output node for coupling to a load and providing a first voltage level at a predetermined impedance, the first voltage level corresponding to a logic high level, and providing a second voltage level at the predetermined impedance, the second voltage level corresponding to a logic low level, and presenting a high impedance state;
a first switched resistive element coupled to the output node and also coupled to a first voltage source;
a second switched resistive element coupled to the output node and also coupled to a ground potential;
a third switched resistive element coupled to the output node and also coupled to the ground potential;
a first control line coupled to the first switched resistive element, the first control line for actuating the first switched resistive element;
a second control line coupled to the second switched resistive element, the second control line for actuating the second switched resistive element;
a third control line coupled to the third switched resistive element, the third control line for actuating the third switched resistive element;
and
a predriver having a first node coupled to the first control line and a second node coupled to the second control line, the predriver adapted to provide a predetermined edge rate;
and
wherein the load is a resistive load coupled to a third voltage source and wherein the first voltage level, the second voltage level and the predetermined impedance remain substantially constant with variations in manufacturing process, variations in the first voltage source and variations in operating temperature.

8 more elements

A driver comprising:

an output section, including:
an output node;
a plurality of P-nodes;
a first plurality of P-channel transistors, each P-channel transistor of the first plurality of P-channel transistors having a source coupled to a supply voltage and a drain coupled to the output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the first plurality of P-channel transistors;
a plurality of N-nodes;
a first plurality of N-channel transistors, each N-channel transistor of the first plurality of N-channel transistors having a drain coupled to the output node and a source coupled to a ground potential relative to the supply voltage wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the first plurality of N-channel transistors;
and
a second plurality of N-channel transistors, each N-channel transistor of the second plurality of N-channel transistors having a drain coupled to the output node and a source coupled to the ground potential wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the second plurality of N-channel transistors;
and
a first predriver section including:
a P-output node;
a second plurality of P-channel transistors, each P-channel transistor of the second plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the P-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the second plurality of P-channel transistors;
a third plurality of N-channel transistors, each N-channel transistor of the third plurality of N-channel transistors having a drain coupled to the P-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the third plurality of N-channel transistors;
an N-output node;
a third plurality of P-channel transistors, each P-channel transistor of the third plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the N-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the third plurality of P-channel transistors;
and
a fourth plurality of N-channel transistors, each N-channel transistor of the fourth plurality of N-channel transistors having a drain coupled to the N-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fourth plurality of N-channel transistors;
and
wherein the P-output node is coupled to the source of each P-channel transistor of the first plurality of P-channel transistors and further wherein the N-output node is coupled to the source of each N-channel transistor of the first plurality of N-channel transistors;
and
a second predriver section including:
a T-node;
a fourth plurality of P-channel transistors, each P-channel transistor of the fourth plurality of P-channel transistors having a source coupled to the supply voltage and a drain coupled to the T-node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the fourth plurality of P-channel transistors;
and
a fifth plurality of N-channel transistors, each N-channel transistor of the fifth plurality of N-channel transistors having a drain coupled to the T-node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fifth plurality of N-channel transistors;
and
wherein the T-node is coupled to the source of each of the second plurality of N-channel transistors of the output section.

24 more elements

Dependencies are inferred from the claim text.

Description7,733 words

Summary1,774 words

#The present invention relates generally to data communications between electronic devices and particularly, but not by way of limitation, to a driver for high speed data communications.

#Of the many trends apparent in the electronic industry, two noteworthy examples include increased processor speeds and reduced power consumption. The trend toward increased processor speed enables execution of sophisticated and complex calculations at ever increasing speeds. Commensurate with an increased speed is the reduced time available in which digital data may be transmitted and received. The trend toward reduced power consumption facilitates devices operable with battery power or other means having a reduced power supply capacity. Also, low power devices dissipate less heat which further enables a higher component density and yet provide reliable operation.

#The limited amount of available space on an integrated circuit often constrains the placement of components, including such circuits as drivers. A driver circuit is used to receive an input signal and provides an output signal on interconnect lines. In many applications, a driver requires connections to multiple power supplies. For example, power supply traces often are not available or are unduly problematic.

Brief description of the drawings17 figures

#In the drawings, like numerals describe substantially similar components throughout the several views, with alphabetic suffixes indicating different instances of similar components.

#FIG. 1 is a schematic diagram illustrating generally an output driver coupled to a transmission line.

#FIG. 2A is a schematic diagram illustrating generally a portion of the present system and the environment in which it operates.

Detailed description5,678 words

#In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

#FIG. 1 depicts a schematic showing driver circuit 10. Driver circuit 10 is shown coupled to transmission line 26 terminating at load resistor 28, herein denoted as RTERM. A typical value for RTERM is 45 ohms. Transmission line 26 may be an interconnect bus. The other leg of resistor 28 is coupled to supply voltage 30, herein marked VTT.

#Driver circuit 10 may employ GTL technology as described in U.S. Pat. No. 5,023,488 to William F. Gunning, which is herein incorporated by reference. The +− symbol of GTL+ denotes the use of a PFET pull up transistor coupled to the drain of the NFET pull down transistor at the output of the driver.

Abstract

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Claims21

Abstract

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Drawings

Claims21

Description7,733 words

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Classification2 codes

Life of this patent

Description7,733 words