Apparatus and method for reducing reflexions in a memory bus system
AssigneeInfineon Technologies AG
InventorSimon Muff
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AssigneeInfineon Technologies AG
InventorSimon Muff
Estimating the term…
The present invention relates to an apparatus and a method for reducing reflexions in a bus for transmitting data. The device comprises an output, which is connected to an input of the bus, a device for sending a test signal into the input of the bus (102), the device for sending being connected to the output, a device for receiving reflexions from the bus, which is connected to the output, and a device for evaluating the reflexions from the bus, in order to supply an evaluation result, and for setting an impedance at the output as a function of the evaluation result, in order to reduce the reflexions from the bus.
Apparatus for reducing reflexions in a bus for transmitting data, having the following features:
Method for reducing reflexions in a bus for transmitting data, having the following features:
Dependencies are inferred from the claim text.
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Electrical coupling: bus impedance matching, e.g. termination
Computing and data processing
Term ended 12 Jun 2022 (estimated)
This application claims the benefit of German application number 101 24 176.3, filed May 17, 2001, currently pending, the disclosure of which is hereby incorporated by reference in its entirety.
The present invention relates to an apparatus and a method for reducing reflexions in a memory bus system in which data are sent and received.
In conventional buses, such as memory subsystem buses in computer systems, reflexions or multiple reflexions typically occur in the bus during the sending and receiving of data at the connecting points of components such as, for example, memory components. Further causes for reflexions are, in general, branches of the bus with a different load, changes in impedance inside the bus and, in general, the topology of the bus.
Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the attached drawings, in which:
FIG. 1 shows an exemplary embodiment of an apparatus in accordance with the present invention;
FIG. 2 shows the frequency-dependent behavior of the impedance at the output of the apparatus of FIG. 1; and
FIG. 1 shows an exemplary embodiment of an apparatus according to the invention for reducing reflexions in a bus, in which data can be transmitted. The apparatus 100 for reducing reflexions in a bus 102 is connected to an input of the bus 102 via an output 104. The bus 102 is preferably a memory subsystem bus to which memory components (130), preferably dynamic random access memory (DRAM) memory elements can be connected.
The apparatus 100 has a device 106 for sending a test signal into the input of the bus 102, the device 106 for sending being connected to the output 104. The device 106 for sending is preferably a driver for driving test signals or data signals into the bus 102. The test signal is preferably a digital signal which preferably has a predefined bit pattern. The predefined bit pattern is a function of the system and preferably includes instructions with the aid of which the apparatus 100 is calibrated in order to reduce reflexions in the bus 102.
The apparatus 100 for reducing reflexions further has a device 108 for receiving reflexions from the bus 102, which is connected to the output 104. The device for receiving is preferably a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at the device 108 for receiving.