Techniques for testing embedded cores in multi-core integrated circuit designs

An integrated circuit having multiple embedded cores, each of the embedded cores including a test access port, the integrated circuit further comprising:

• a demultiplexer connected to a chip-level test input signal, said demultiplexer having a plurality of outputs, each of said outputs connected to the test access port of one of the embedded cores;
• a multiplexer connected to a chip-level test output signal, said multiplexer having a plurality of inputs, each of said inputs connected to the test access port of one of the embedded cores;
• and
• a select register connected to said demultiplexer and to said multiplexer, said select register routing the input of said demultiplexer to the output of said demultiplexer and the input of said multiplexer to the output of said multiplexer according to a plurality of bits loaded into the select register such that the selected output and the selected input are connected to the same embedded core.

An integrated circuit having multiple embedded cores, each of the embedded cores including a test access port the integrated circuit further comprising:

• a demultiplexer having outputs connected to the test access ports of a first group of embedded cores;
• a top-level demultiplexer connected to a chip-level test input signal, said demultiplexer having a plurality of top-level demultiplexer outputs connected to the test access port of a second group of embedded cores distinct from said first group of embedded cores and to an input of said demultiplexer;
• a multiplexer having inputs received from the test access ports of said first group of embedded cores;
• a top-level multiplexer connected to a chip-level test output signal, said top-level multiplexer having a plurality of top-level multiplexer inputs connected to the test access ports said second group of embedded cores and to an output of said multiplexer;
• a first select register connected to said demultiplexer and to said multiplexer, said first select register routing the input of said demultiplexer to the output of said demultiplexer and the input of said multiplexer to the output of said multiplexer such that the selected output and the selected input are connected to the same embedded core;
• and
• a second select register connected to said top-level demultiplexer and to said top-level multiplexer, said second select register routing the input of top-level demultiplexer to the output of said top-level demultiplexer and the input of said top-level multiplexer to the output of said top-level multiplexer such that the selected top-level demultiplexer output and the selected top-level multiplexer input are connected either to the same embedded core or to said demultiplexer and multiplexer, respectively.

A method of testing circuit blocks embedded within an integrated circuit, the method comprising the steps of:

• loading address data bits corresponding to a selected circuit block into at least one select register;
• receiving at least one test input data signal for a selected circuit block, based on the address bits of said at least one select register;
• demultiplexing the at least one test input data signal;
• sending the at least one demultiplexed test input data signal to the selected circuit block based on the address bits of the at least one select register;
• receiving test result signals from the circuit blocks;
• and
• multiplexing the test result signals based upon the address bits of the at least one select register.