US 6,686,663 B2 · Semiconductor device and a method of manufacturing the same

Abstract

Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims15

Dependent claims

A memory card comprising:

a substrate having a main surface, a rear surface opposed of the main surface, a plurality of electrodes on the main surface and a plurality of external connecting terminals on the rear surface;
a first semiconductor chip having a main surface and a plurality of bonding pads formed along one side of the main surface, the first semiconductor chip being mounted on the main surface of the substrate;
a second semiconductor chip having a main surface and a plurality of bonding pads formed along one side of the main surface, the second semiconductor chip being stacked over the main surface of the first semiconductor chip;
first wires electrically connecting respective ones of the bonding pads of the first semiconductor chip with corresponding ones of the plurality of electrodes, the first wires being connected at first connecting portions of the plurality of electrodes, respectively;
second wires electrically connecting respective ones of the bonding pads of the second semiconductor chip with corresponding ones of the plurality of electrodes, the second wires being connected at second connecting portions of the plurality of electrodes, respectively;
and
a resin sealing the first semiconductor chip, the second semiconductor chip, the first wires, the second wires and the plurality of electrodes;
wherein the second semiconductor chip is stacked over the main surface of the first semiconductor chip while being offset in a direction parallel to the one side of said first semiconductor chip and in a direction perpendicular thereto;
wherein the first semiconductor chip and second semiconductor chip have a circuit of the same function formed thereon and a same arrangement of the bonding pads;
wherein the first semiconductor chip and the second semiconductor chip are arranged such that the one sides thereof, along which the bonding pads thereof are formed, are facing towards the plurality of electrodes, respectively;
wherein the first connecting portions are electrically connected with the second connecting portions via the electrodes of the substrate;
wherein the second connecting portions are arranged farther from the one side of the first semiconductor chip than the first connecting portions;
and wherein distances between each of the first connecting portions and corresponding ones of the second connecting portions in a direction perpendicular to the one side of the first semiconductor chip is larger than distances between them in a direction parallel to the one side of the first semiconductor chip.

10 more elements

Dependencies are inferred from the claim text.

Description4,771 words

Summary1,188 words

#The present invention relates to a semiconductor device, and to a technique for manufacturing the same; and, more particularly, the invention relates to a technique which is effective when applied to a semiconductor device having a plurality of semiconductor chips stacked therein, and which is resin-sealed in a single package.

#As one of the measures for increasing the capacity of a memory LSI, such as a flash memory or a DRAM (dynamic random access memory), a variety of memory module structures, which are manufactured by stacking semiconductor chips, each having such a memory LSI formed thereon, and then sealing them in a single package, have been proposed.

#For example, Japanese Patent Application Laid-Open No. Hei 4(1992)-302164 discloses a package structure obtained by stacking, stepwise, in one package, a plurality of semiconductor chips having the same function and the same size via an insulating layer, and electrically connecting a bonding pad which is exposed at the stepped portion of each of the semiconductor chips with an inner lead of the package through a wire.

Brief description of the drawings19 figures

#FIG. 1 is a plan view illustrating the outer appearance of the semiconductor device according to one embodiment of the present invention;

#FIG. 2 is a cross-sectional view taken along a line A—A of FIG. 1;

#FIG. 3 is a plan view illustrating the base substrate of the semiconductor device of FIG. 1;

Detailed description3,164 words

#Embodiments of the present invention will hereinafter be described in detail based on the accompanying drawings. In all the drawings which illustrate the embodiments of the present invention, members having a like function will be identified by like reference numerals and overlapping descriptions thereof will be omitted.

#(Embodiment 1)

#FIG. 1 is a plan view illustrating the outer appearance of the semiconductor device according to this Embodiment; FIG. 2 is a cross-sectional view taken along the longitudinal direction (a line A—A) of this semiconductor device; and FIG. 3 is a plan view illustrating the base substrate of this semiconductor device.

Facts

Application

10/194,224Filed 15 Jul 2002 · continuation

Priority

JP 2000-02280231 Jan 2000

Published

US 2002/0180060 A15 Dec 2002

Granted

3 Feb 2004

Term ended

26 Jan 2021

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification35 codes

H10W 90/00
Package configurations
B82Y 10/00
Nanotechnology for information processing, storage or transmission
G06K 19/077
With integrated circuit chips: constructional details, e.g. mounting of circuits in the carrier
G06K 19/07732
Physical layout of the record carrier: the record carrier having a housing or construction similar to well-known portable memory devices, such as…

Timeline

31 Jan 2000Priority claimedJP 2000-022802
15 Jul 2002Application filedUS 10/194,224
5 Dec 2002PublishedUS 2002/0180060 A1
3 Feb 2004GrantedUS 6,686,663 B2
19 Sep 2006Assigned to Akita Electronics Systems Co., Ltd.change of name
19 Sep 2006Assigned to Akita Electronics Systems Co., Ltd.assignment of assignor's interest
14 Dec 2006Assigned to Elpida Memory, Inc.assignment of assignor's interest
15 May 2012Assigned to Apple Inc.security agreement
29 Jul 2013Assigned to Elpida Memory Inc.security agreement
24 Feb 2014Assigned to Elpida Memory, Inc.release of security interest
15 May 2014Assigned to Ps4 Luxco S.A.R.L.assignment of assignor's interest
24 Aug 2016Assigned to Ps5 Luxco S.A.R.L.assignment of assignor's interest
24 Aug 2016Assigned to Longitude Semiconductor S.A.R.L.change of name
21 Aug 2018Assigned to Longitude Licensing Limitedassignment of assignor's interest
26 Jan 2021Term endedEstimated

Semiconductor device and a method of manufacturing the same

Life of this patent

Semiconductor device and a method of manufacturing the same

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims15

Description4,771 words

Drawings

Classification35 codes

Life of this patent

Description4,771 words