US 6,686,656 B1 · Integrated multi-chip chip scale package

Abstract

A vertically integrated chip scale package (CSP) assembly comprising two or more single chip package subassemblies having an upper level CSP subassembly superimposed directly above a lower level CSP subassembly. The lower-most CSP subassembly in the vertical stack contains an array of solder balls for interconnection to a printed wiring board. The vertical electrical connection between the upper and lower level package subassemblies is accomplished by using wire bonding from perimeter wire bonding pads located on an upper level substrate extension to matching perimeter wire bonding pads located on a lower level substrate extension that is longer in length than the upper level substrate extension. The stacked package subassemblies are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant for protection. The assembled vertical stack has the appearance of a single CSP but is shorter in height than two individual packages that are stacked together with solder ball interconnects located therebetween.

Claims18

Dependent claims

An integrated chip scale package assembly comprising at least first and second chip scale packages disposed one above the other, wherein the first of said first and second chip scale packages includes an integrated circuit chip,

a substrate to which said integrated circuit chip is bonded, said substrate having top and bottom sides and an extension that projects outwardly and beyond the integrated circuit chip,
a plurality of solder ball bonding pads located at the bottom side of the substrate,
a plurality of perimeter wire bonding pads located on the substrate extension,
electrically conductive signal traces located on said substrate and interconnected between said integrated circuit chip and said plurality of perimeter wire bonding pads, and
an array of solder ball interconnects attached to respective ones of said plurality of solder ball bonding pads at the bottom side of said substrate by which said first chip scale package is adapted to be attached to a printed wiring board.

2 more elements

An integrated scale package assembly comprising a plurality of chip scale package subassemblies that are arranged in a vertical stack one above the other, each of said plurality of chip scale package subassemblies having an integrated circuit chip mounted on a substrate such that the substrate of an upper one of said chip scale package subassemblies in the vertical stack is mounted directly on top of the integrated circuit chip of an adjacent lower one of said chip scale package subassemblies, each substrate having a plurality of perimeter wire bonding pads and a plurality of electrically conductive signal traces connected between said plurality of perimeter wire bonding pads and the integrated circuit chip mounted on said substrate,

a plurality of solder ball bonding pads located on the substrate of the bottom-most one of said vertical stack of chip scale package subassemblies, and
an array of solder ball interconnects attached to respective ones of said plurality of solder ball bonding pads of said bottom-most chip scale package subassembly by which said vertical stack is adapted to be attached to a printed wiring board.

Dependencies are inferred from the claim text.

Integrated multi-chip chip scale package

Life of this patent

Integrated multi-chip chip scale package

Life of this patent

Abstract

Claims18