Gate structure with independently tailored vertical doping profile
AssigneeInternational Business Machines Corporation
InventorsOmer Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens
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Abstract
A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
Claims14
A gate structure for a semiconductor transistor, comprising:
- a lower polysilicon region doped at a first concentration;
- an upper polysilicon region doped at a second concentration, said second concentration different than said first concentration;
- and
- a conductive barrier layer, disposed between said lower and said upper polysilicon regions;
- wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
A metal oxide semiconductor (MOS) transistor device, comprising:
- a source diffusion region and a drain diffusion region;
- and
- a gate stack structure disposed upon a gate dielectric, said gate stack structure further comprising:
- a lower polysilicon region doped at a first dopant concentration;
- a conductive barrier layer, disposed on said lower polysilicon region;
- and
- an upper polysilicon region, disposed on said conductive barrier layer, said upper polysilicon region doped at a second concentration, said second concentration being different than said first concentration;
- wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
Dependencies are inferred from the claim text.