US 6,686,636 B2Granted

Semiconductor raised source-drain structure

AssigneeMicron Technology, Inc.

InventorsFernando Gonzalez, Chandra Mouli

Life of this patent

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Abstract

A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The semiconductor structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain. The system also includes a processor and a bus connecting the processor and the memory device.

Claims25

Dependent claims

A system, comprising:

a memory device having at least one semiconductor structure, wherein said memory device is in communication with at least one random access memory, said structure including:
a raised source;
a raised drain;
and
a gate located between said source and said drain;
a first capping layer in communication with at least a portion of said gate and said source;
a first portion of a gate oxide region in communication with at least a portion of said gate and said source;
said source, said gate, said first capping layer, and said first portion of said gate oxide region defining a first gap therein, said first gap having one of a gas and a vacuum therein, wherein no dielectric material is positioned between said first gap and any one of said gate, said source, said first capping layer, and said first portion of said gate oxide region;
a second capping layer in communication with at least a portion of said gate and said drain;
a second portion of said gate oxide region in communication with at least a portion of said gate and said drain;
and
said drain, said gate, said second capping layer, and said second portion of said gate oxide region defining a second gap therein, said second gap having one of a gas and a vacuum therein, wherein no dielectric material is positioned between said second gap and any one of said gate, said drain, said second capping layer, and said second portion of said gate oxide region;
a processor;
and
a bus connecting said processor and said memory device.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/008,650Filed 9 Nov 2001 · division
Priority: 1 Sep 1998
Published: US 2002/0041001 A111 Apr 2002
Granted: 3 Feb 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/679
Gate sidewall spacers: comprising air gaps
H10D 30/0218
Of FETs having insulated gates [IGFET]: having pocket halo regions selectively formed at the sides of the gates
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 64/0111
Of electrodes ohmically coupled to a semiconductor: to Group IV semiconductors

Family

Application09/144,662Parent of this division · filed 1 Sep 1998
US 2002/0041001 A1Pre-grant publication · published 11 Apr 2002
US 2001/0022381 A1Published application
US 6,693,335 B2Related patent
US 6,686,636 B2This patent

From the US filing history. Foreign family members aren’t listed.