Semiconductor device, memory cell, and processes for forming them

A memory cell comprising:

• a substrate;
• a field isolation region overlying a portion of the substrate
• a gate dielectric layer overlying a different portion of the substrate;
• and
• a first conductive member overlying the field isolation region and the gate dielectric layer, wherein:
• the first conductive member includes an interconnect section and a gate electrode section;
• and
• a first silicide region lies on the interconnect section of the first conductive member but no silicide lies on the gate electrode section of the first conductive member.

A semiconductor device comprising:

• a first conductive region lying at a first elevation;
• a second conductive region lying at a second elevation that is higher than the first elevation;
• a first insulating film overlying the first and second conductive regions, wherein the first insulating film includes a material selected from a group consisting of a graded nitride, a metal nitride, a refractory metal oxide, and a low-k dielectric;
• a second insulating film overlying the first insulating film and having a thickness of at least approximately 1000 angstroms, wherein the second insulating film is capable of being removed at different rate compared to the first insulating film;
• an opening extending through the first and second insulating films over the first and second conductive regions;
• and
• an interconnect electrically connected to at least one of the first and second conductive regions, wherein the interconnect substantially fills the opening.

A semiconductor device including a memory array that comprises:

• components formed at a primary surface of a substrate;
• a first insulating layer overlying the components;
• first level interconnects overlying the first insulating layer, wherein the first level interconnects are electrically connected to power supply electrodes;
• a second insulating layer overlying the first level interconnects;
• and
• second level interconnects overlying the second insulating layer, wherein within the memory array:
• the second level interconnects include bit lines;
• and
• the second level interconnects lie at an elevation higher than all interconnects that supply power to memory cells within the memory array.